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Commit 61624caf authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
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ARM: shmobile: r8a7790: Add IRQC clock to device tree



Link the external IRQ controller irqc0 to the IRQC module clock, so it
can be power managed using that clock.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 1c2a7eb7
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+9 −0
Original line number Original line Diff line number Diff line
@@ -252,6 +252,7 @@
			     <0 1 IRQ_TYPE_LEVEL_HIGH>,
			     <0 1 IRQ_TYPE_LEVEL_HIGH>,
			     <0 2 IRQ_TYPE_LEVEL_HIGH>,
			     <0 2 IRQ_TYPE_LEVEL_HIGH>,
			     <0 3 IRQ_TYPE_LEVEL_HIGH>;
			     <0 3 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
	};
	};


	dmac0: dma-controller@e6700000 {
	dmac0: dma-controller@e6700000 {
@@ -1158,6 +1159,14 @@
				"iic0", "pciec", "iic1", "ssusb", "cmt1",
				"iic0", "pciec", "iic1", "ssusb", "cmt1",
				"usbdmac0", "usbdmac1";
				"usbdmac0", "usbdmac1";
		};
		};
		mstp4_clks: mstp4_clks@e6150140 {
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
			clocks = <&cp_clk>;
			#clock-cells = <1>;
			clock-indices = <R8A7790_CLK_IRQC>;
			clock-output-names = "irqc";
		};
		mstp5_clks: mstp5_clks@e6150144 {
		mstp5_clks: mstp5_clks@e6150144 {
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+3 −0
Original line number Original line Diff line number Diff line
@@ -79,6 +79,9 @@
#define R8A7790_CLK_USBDMAC0		30
#define R8A7790_CLK_USBDMAC0		30
#define R8A7790_CLK_USBDMAC1		31
#define R8A7790_CLK_USBDMAC1		31


/* MSTP4 */
#define R8A7790_CLK_IRQC		7

/* MSTP5 */
/* MSTP5 */
#define R8A7790_CLK_AUDIO_DMAC1		1
#define R8A7790_CLK_AUDIO_DMAC1		1
#define R8A7790_CLK_AUDIO_DMAC0		2
#define R8A7790_CLK_AUDIO_DMAC0		2