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Commit 612b8507 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT (v2)
  drm/i915: no lvds quirk for AOpen MP45
  drm/i915: Force explicit bpp selection for intel_dp_link_required
  drm/radeon: do not continue after error from r600_ib_test
  drivers/gpu/drm/drm_ioc32.c: initialize all fields
  drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT
  drm/i915:: Disable FBC on SandyBridge
parents af5feae3 28a4d567

drivers/gpu/drm/drm_ioc32.c

+2 −1
Original line number Diff line number Diff line
@@ -315,7 +315,8 @@ static int compat_drm_getclient(struct file *file, unsigned int cmd, 
	if (err)

		return err;



	if (__get_user(c32.auth, &client->auth)

	if (__get_user(c32.idx, &client->idx)

	    || __get_user(c32.auth, &client->auth)

	    || __get_user(c32.pid, &client->pid)

	    || __get_user(c32.uid, &client->uid)

	    || __get_user(c32.magic, &client->magic)

drivers/gpu/drm/i915/intel_display.c

+5 −3
Original line number Diff line number Diff line
@@ -1872,7 +1872,7 @@ static void intel_update_fbc(struct drm_device *dev) 
	if (enable_fbc < 0) {

		DRM_DEBUG_KMS("fbc set to per-chip default\n");

		enable_fbc = 1;

		if (INTEL_INFO(dev)->gen <= 5)

		if (INTEL_INFO(dev)->gen <= 6)

			enable_fbc = 0;

	}

	if (!enable_fbc) {
@@ -5307,6 +5307,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 
		}

	}



	pipeconf &= ~PIPECONF_INTERLACE_MASK;

	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {

		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;

		/* the chip adds 2 halflines automatically */
@@ -5317,7 +5318,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 
		adjusted_mode->crtc_vsync_end -= 1;

		adjusted_mode->crtc_vsync_start -= 1;

	} else

		pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */

		pipeconf |= PIPECONF_PROGRESSIVE;



	I915_WRITE(HTOTAL(pipe),

		   (adjusted_mode->crtc_hdisplay - 1) |
@@ -5902,6 +5903,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
		}

	}



	pipeconf &= ~PIPECONF_INTERLACE_MASK;

	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {

		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;

		/* the chip adds 2 halflines automatically */
@@ -5912,7 +5914,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
		adjusted_mode->crtc_vsync_end -= 1;

		adjusted_mode->crtc_vsync_start -= 1;

	} else

		pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */

		pipeconf |= PIPECONF_PROGRESSIVE;



	I915_WRITE(HTOTAL(pipe),

		   (adjusted_mode->crtc_hdisplay - 1) |

drivers/gpu/drm/i915/intel_dp.c

+5 −15
Original line number Diff line number Diff line
@@ -208,17 +208,8 @@ intel_dp_link_clock(uint8_t link_bw) 
 */



static int

intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock, int check_bpp)

intel_dp_link_required(int pixel_clock, int bpp)

{

	struct drm_crtc *crtc = intel_dp->base.base.crtc;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int bpp = 24;



	if (check_bpp)

		bpp = check_bpp;

	else if (intel_crtc)

		bpp = intel_crtc->bpp;



	return (pixel_clock * bpp + 9) / 10;

}
@@ -245,12 +236,11 @@ intel_dp_mode_valid(struct drm_connector *connector, 
			return MODE_PANEL;

	}



	mode_rate = intel_dp_link_required(intel_dp, mode->clock, 0);

	mode_rate = intel_dp_link_required(mode->clock, 24);

	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);



	if (mode_rate > max_rate) {

			mode_rate = intel_dp_link_required(intel_dp,

							   mode->clock, 18);

			mode_rate = intel_dp_link_required(mode->clock, 18);

			if (mode_rate > max_rate)

				return MODE_CLOCK_HIGH;

			else
@@ -683,7 +673,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 
	int lane_count, clock;

	int max_lane_count = intel_dp_max_lane_count(intel_dp);

	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;

	int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 0;

	int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;

	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };



	if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
@@ -701,7 +691,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 
		for (clock = 0; clock <= max_clock; clock++) {

			int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);



			if (intel_dp_link_required(intel_dp, mode->clock, bpp)

			if (intel_dp_link_required(mode->clock, bpp)

					<= link_avail) {

				intel_dp->link_bw = bws[clock];

				intel_dp->lane_count = lane_count;

drivers/gpu/drm/i915/intel_lvds.c

+8 −0
Original line number Diff line number Diff line
@@ -692,6 +692,14 @@ static const struct dmi_system_id intel_no_lvds[] = { 
			DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

                .ident = "AOpen i45GMx-I",

                .matches = {

                        DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),

                        DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),

                },

        },

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Aopen i945GTt-VFA",

drivers/gpu/drm/radeon/evergreen.c

+1 −0
Original line number Diff line number Diff line
@@ -3191,6 +3191,7 @@ static int evergreen_startup(struct radeon_device *rdev) 
	if (r) {

		DRM_ERROR("radeon: failed testing IB (%d).\n", r);

		rdev->accel_working = false;

		return r;

	}



	r = r600_audio_init(rdev);