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Commit 610e1283 authored by Niklas Cassel's avatar Niklas Cassel Committed by Rob Herring
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bindings: PCI: artpec: correct pci binding example 



 - Increase config size. When using a PCIe switch,
   the previous config size only had room for one device.
 - Add bus range. Inherited optional property.
 - Map downstream I/O to PCI address 0. We can map it to any
   address, but let's be consistent with other drivers.

Signed-off-by: default avatarNiklas Cassel <niklas.cassel@axis.com>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 58397832

Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt

+4 −3
Original line number Diff line number Diff line
@@ -24,16 +24,17 @@ Example: 
		compatible = "axis,artpec6-pcie", "snps,dw-pcie";

		reg = <0xf8050000 0x2000

		       0xf8040000 0x1000

		       0xc0000000 0x1000>;

		       0xc0000000 0x2000>;

		reg-names = "dbi", "phy", "config";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

			  /* downstream I/O */

		ranges = <0x81000000 0 0x00010000 0xc0010000 0 0x00010000

		ranges = <0x81000000 0 0 0xc0002000 0 0x00010000

			  /* non-prefetchable memory */

			  0x82000000 0 0xc0020000 0xc0020000 0 0x1ffe0000>;

			  0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;

		num-lanes = <2>;

		bus-range = <0x00 0xff>;

		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "msi";

		#interrupt-cells = <1>;