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Commit 60c5ea2d authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: mask the video DIP frequency when changing it 



Better safe than sorry. Currently we never change the frequency and
use the same for every infoframe type, so the only way to reproduce a
bug would be with the BIOS doing something.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ecb97851

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -1711,6 +1711,7 @@ 
#define   VIDEO_DIP_FREQ_ONCE		(0 << 16)

#define   VIDEO_DIP_FREQ_VSYNC		(1 << 16)

#define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)

#define   VIDEO_DIP_FREQ_MASK		(3 << 16)



/* Panel power sequencing */

#define PP_STATUS	0x61200

drivers/gpu/drm/i915/intel_hdmi.c

+3 −0
Original line number Diff line number Diff line
@@ -164,6 +164,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder, 
	}



	val |= intel_infoframe_enable(frame);

	val &= ~VIDEO_DIP_FREQ_MASK;

	val |= intel_infoframe_frequency(frame);



	I915_WRITE(VIDEO_DIP_CTL, val);
@@ -203,6 +204,7 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder, 
	}



	val |= intel_infoframe_enable(frame);

	val &= ~VIDEO_DIP_FREQ_MASK;

	val |= intel_infoframe_frequency(frame);



	I915_WRITE(reg, val);
@@ -236,6 +238,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, 
	}



	val |= intel_infoframe_enable(frame);

	val &= ~VIDEO_DIP_FREQ_MASK;

	val |= intel_infoframe_frequency(frame);



	I915_WRITE(reg, val);