Commit 5fdd1b56 authored Nov 22, 2013 by Seung-Woo Kim Committed by Tomasz Figa Dec 30, 2013

clk: samsung: exynos4: Correct SRC_MFC register



The SRC_MFC register offset was incorrect, which could cause have caused
wrong calculation of rate of sclk_mfc clock, that could in turn lead to
incorrect operation of MFC. This patch corrects it.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>

parent 6ce4eac1

drivers/clk/samsung/clk-exynos4.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -39,7 +39,7 @@
		#define SRC_TOP1 0xc214
		#define SRC_CAM 0xc220
		#define SRC_TV 0xc224
		#define SRC_MFC 0xcc28
		#define SRC_MFC 0xc228
		#define SRC_G3D 0xc22c
		#define E4210_SRC_IMAGE 0xc230
		#define SRC_LCD0 0xc234