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Commit 5fc3aeeb authored by yanyang1's avatar yanyang1 Committed by Alex Deucher
Browse files

drm/amdgpu: rename amdgpu_ip_funcs to amd_ip_funcs (v2) 



The structure is renamed and moved to amd_shared.h to make
the component independent.  This makes it easier to add
new components in the future.

v2: fix include path

Reviewed-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: default avataryanyang1 <young.yang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dcc357e6

drivers/gpu/drm/amd/amdgpu/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
# Makefile for the drm device driver.  This driver provides support for the

# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.



ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/asic_reg

ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/asic_reg \

	-Idrivers/gpu/drm/amd/include



amdgpu-y := amdgpu_drv.o

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+9 −66
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 


#include <drm/drm_gem.h>



#include "amd_shared.h"

#include "amdgpu_family.h"

#include "amdgpu_mode.h"

#include "amdgpu_ih.h"
@@ -205,86 +206,28 @@ enum amdgpu_thermal_irq { 
	AMDGPU_THERMAL_IRQ_LAST

};



/*

 * IP block functions

 */

enum amdgpu_ip_block_type {

	AMDGPU_IP_BLOCK_TYPE_COMMON,

	AMDGPU_IP_BLOCK_TYPE_GMC,

	AMDGPU_IP_BLOCK_TYPE_IH,

	AMDGPU_IP_BLOCK_TYPE_SMC,

	AMDGPU_IP_BLOCK_TYPE_DCE,

	AMDGPU_IP_BLOCK_TYPE_GFX,

	AMDGPU_IP_BLOCK_TYPE_SDMA,

	AMDGPU_IP_BLOCK_TYPE_UVD,

	AMDGPU_IP_BLOCK_TYPE_VCE,

};



enum amdgpu_clockgating_state {

	AMDGPU_CG_STATE_GATE = 0,

	AMDGPU_CG_STATE_UNGATE,

};



enum amdgpu_powergating_state {

	AMDGPU_PG_STATE_GATE = 0,

	AMDGPU_PG_STATE_UNGATE,

};



struct amdgpu_ip_funcs {

	/* sets up early driver state (pre sw_init), does not configure hw - Optional */

	int (*early_init)(struct amdgpu_device *adev);

	/* sets up late driver/hw state (post hw_init) - Optional */

	int (*late_init)(struct amdgpu_device *adev);

	/* sets up driver state, does not configure hw */

	int (*sw_init)(struct amdgpu_device *adev);

	/* tears down driver state, does not configure hw */

	int (*sw_fini)(struct amdgpu_device *adev);

	/* sets up the hw state */

	int (*hw_init)(struct amdgpu_device *adev);

	/* tears down the hw state */

	int (*hw_fini)(struct amdgpu_device *adev);

	/* handles IP specific hw/sw changes for suspend */

	int (*suspend)(struct amdgpu_device *adev);

	/* handles IP specific hw/sw changes for resume */

	int (*resume)(struct amdgpu_device *adev);

	/* returns current IP block idle status */

	bool (*is_idle)(struct amdgpu_device *adev);

	/* poll for idle */

	int (*wait_for_idle)(struct amdgpu_device *adev);

	/* soft reset the IP block */

	int (*soft_reset)(struct amdgpu_device *adev);

	/* dump the IP block status registers */

	void (*print_status)(struct amdgpu_device *adev);

	/* enable/disable cg for the IP block */

	int (*set_clockgating_state)(struct amdgpu_device *adev,

				     enum amdgpu_clockgating_state state);

	/* enable/disable pg for the IP block */

	int (*set_powergating_state)(struct amdgpu_device *adev,

				     enum amdgpu_powergating_state state);

};



int amdgpu_set_clockgating_state(struct amdgpu_device *adev,

				  enum amdgpu_ip_block_type block_type,

				  enum amdgpu_clockgating_state state);

				  enum amd_ip_block_type block_type,

				  enum amd_clockgating_state state);

int amdgpu_set_powergating_state(struct amdgpu_device *adev,

				  enum amdgpu_ip_block_type block_type,

				  enum amdgpu_powergating_state state);

				  enum amd_ip_block_type block_type,

				  enum amd_powergating_state state);



struct amdgpu_ip_block_version {

	enum amdgpu_ip_block_type type;

	enum amd_ip_block_type type;

	u32 major;

	u32 minor;

	u32 rev;

	const struct amdgpu_ip_funcs *funcs;

	const struct amd_ip_funcs *funcs;

};



int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,

				enum amdgpu_ip_block_type type,

				enum amd_ip_block_type type,

				u32 major, u32 minor);



const struct amdgpu_ip_block_version * amdgpu_get_ip_block(

					struct amdgpu_device *adev,

					enum amdgpu_ip_block_type type);

					enum amd_ip_block_type type);



/* provided by hw blocks that can move/clear data.  e.g., gfx or sdma */

struct amdgpu_buffer_funcs {

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+25 −25
Original line number Diff line number Diff line
@@ -1081,14 +1081,14 @@ static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { 
};



int amdgpu_set_clockgating_state(struct amdgpu_device *adev,

				  enum amdgpu_ip_block_type block_type,

				  enum amdgpu_clockgating_state state)

				  enum amd_ip_block_type block_type,

				  enum amd_clockgating_state state)

{

	int i, r = 0;



	for (i = 0; i < adev->num_ip_blocks; i++) {

		if (adev->ip_blocks[i].type == block_type) {

			r = adev->ip_blocks[i].funcs->set_clockgating_state(adev,

			r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,

									    state);

			if (r)

				return r;
@@ -1098,14 +1098,14 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 
}



int amdgpu_set_powergating_state(struct amdgpu_device *adev,

				  enum amdgpu_ip_block_type block_type,

				  enum amdgpu_powergating_state state)

				  enum amd_ip_block_type block_type,

				  enum amd_powergating_state state)

{

	int i, r = 0;



	for (i = 0; i < adev->num_ip_blocks; i++) {

		if (adev->ip_blocks[i].type == block_type) {

			r = adev->ip_blocks[i].funcs->set_powergating_state(adev,

			r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,

									    state);

			if (r)

				return r;
@@ -1116,7 +1116,7 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev, 


const struct amdgpu_ip_block_version * amdgpu_get_ip_block(

					struct amdgpu_device *adev,

					enum amdgpu_ip_block_type type)

					enum amd_ip_block_type type)

{

	int i;
@@ -1131,7 +1131,7 @@ const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 
 * amdgpu_ip_block_version_cmp

 *

 * @adev: amdgpu_device pointer

 * @type: enum amdgpu_ip_block_type

 * @type: enum amd_ip_block_type

 * @major: major version

 * @minor: minor version

 *
@@ -1139,7 +1139,7 @@ const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 
 * return 1 if smaller or the ip_block doesn't exist

 */

int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,

				enum amdgpu_ip_block_type type,

				enum amd_ip_block_type type,

				u32 major, u32 minor)

{

	const struct amdgpu_ip_block_version *ip_block;
@@ -1204,7 +1204,7 @@ static int amdgpu_early_init(struct amdgpu_device *adev) 
			adev->ip_block_enabled[i] = false;

		} else {

			if (adev->ip_blocks[i].funcs->early_init) {

				r = adev->ip_blocks[i].funcs->early_init(adev);

				r = adev->ip_blocks[i].funcs->early_init((void *)adev);

				if (r)

					return r;

			}
@@ -1222,15 +1222,15 @@ static int amdgpu_init(struct amdgpu_device *adev) 
	for (i = 0; i < adev->num_ip_blocks; i++) {

		if (!adev->ip_block_enabled[i])

			continue;

		r = adev->ip_blocks[i].funcs->sw_init(adev);

		r = adev->ip_blocks[i].funcs->sw_init((void *)adev);

		if (r)

			return r;

		/* need to do gmc hw init early so we can allocate gpu mem */

		if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) {

		if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {

			r = amdgpu_vram_scratch_init(adev);

			if (r)

				return r;

			r = adev->ip_blocks[i].funcs->hw_init(adev);

			r = adev->ip_blocks[i].funcs->hw_init((void *)adev);

			if (r)

				return r;

			r = amdgpu_wb_init(adev);
@@ -1243,9 +1243,9 @@ static int amdgpu_init(struct amdgpu_device *adev) 
		if (!adev->ip_block_enabled[i])

			continue;

		/* gmc hw init is done early */

		if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC)

		if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)

			continue;

		r = adev->ip_blocks[i].funcs->hw_init(adev);

		r = adev->ip_blocks[i].funcs->hw_init((void *)adev);

		if (r)

			return r;

	}
@@ -1261,12 +1261,12 @@ static int amdgpu_late_init(struct amdgpu_device *adev) 
		if (!adev->ip_block_enabled[i])

			continue;

		/* enable clockgating to save power */

		r = adev->ip_blocks[i].funcs->set_clockgating_state(adev,

								    AMDGPU_CG_STATE_GATE);

		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,

								    AMD_CG_STATE_GATE);

		if (r)

			return r;

		if (adev->ip_blocks[i].funcs->late_init) {

			r = adev->ip_blocks[i].funcs->late_init(adev);

			r = adev->ip_blocks[i].funcs->late_init((void *)adev);

			if (r)

				return r;

		}
@@ -1282,23 +1282,23 @@ static int amdgpu_fini(struct amdgpu_device *adev) 
	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

		if (!adev->ip_block_enabled[i])

			continue;

		if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) {

		if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {

			amdgpu_wb_fini(adev);

			amdgpu_vram_scratch_fini(adev);

		}

		/* ungate blocks before hw fini so that we can shutdown the blocks safely */

		r = adev->ip_blocks[i].funcs->set_clockgating_state(adev,

								    AMDGPU_CG_STATE_UNGATE);

		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,

								    AMD_CG_STATE_UNGATE);

		if (r)

			return r;

		r = adev->ip_blocks[i].funcs->hw_fini(adev);

		r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);

		/* XXX handle errors */

	}



	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

		if (!adev->ip_block_enabled[i])

			continue;

		r = adev->ip_blocks[i].funcs->sw_fini(adev);

		r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);

		/* XXX handle errors */

		adev->ip_block_enabled[i] = false;

	}
@@ -1314,8 +1314,8 @@ static int amdgpu_suspend(struct amdgpu_device *adev) 
		if (!adev->ip_block_enabled[i])

			continue;

		/* ungate blocks so that suspend can properly shut them down */

		r = adev->ip_blocks[i].funcs->set_clockgating_state(adev,

								    AMDGPU_CG_STATE_UNGATE);

		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,

								    AMD_CG_STATE_UNGATE);

		/* XXX handle errors */

		r = adev->ip_blocks[i].funcs->suspend(adev);

		/* XXX handle errors */

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+12 −12
Original line number Diff line number Diff line
@@ -186,7 +186,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
		return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;

	case AMDGPU_INFO_HW_IP_INFO: {

		struct drm_amdgpu_info_hw_ip ip = {};

		enum amdgpu_ip_block_type type;

		enum amd_ip_block_type type;

		uint32_t ring_mask = 0;



		if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
@@ -194,26 +194,26 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 


		switch (info->query_hw_ip.type) {

		case AMDGPU_HW_IP_GFX:

			type = AMDGPU_IP_BLOCK_TYPE_GFX;

			type = AMD_IP_BLOCK_TYPE_GFX;

			for (i = 0; i < adev->gfx.num_gfx_rings; i++)

				ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);

			break;

		case AMDGPU_HW_IP_COMPUTE:

			type = AMDGPU_IP_BLOCK_TYPE_GFX;

			type = AMD_IP_BLOCK_TYPE_GFX;

			for (i = 0; i < adev->gfx.num_compute_rings; i++)

				ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);

			break;

		case AMDGPU_HW_IP_DMA:

			type = AMDGPU_IP_BLOCK_TYPE_SDMA;

			type = AMD_IP_BLOCK_TYPE_SDMA;

			ring_mask = adev->sdma[0].ring.ready ? 1 : 0;

			ring_mask |= ((adev->sdma[1].ring.ready ? 1 : 0) << 1);

			break;

		case AMDGPU_HW_IP_UVD:

			type = AMDGPU_IP_BLOCK_TYPE_UVD;

			type = AMD_IP_BLOCK_TYPE_UVD;

			ring_mask = adev->uvd.ring.ready ? 1 : 0;

			break;

		case AMDGPU_HW_IP_VCE:

			type = AMDGPU_IP_BLOCK_TYPE_VCE;

			type = AMD_IP_BLOCK_TYPE_VCE;

			for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++)

				ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);

			break;
@@ -235,24 +235,24 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
				    min((size_t)size, sizeof(ip))) ? -EFAULT : 0;

	}

	case AMDGPU_INFO_HW_IP_COUNT: {

		enum amdgpu_ip_block_type type;

		enum amd_ip_block_type type;

		uint32_t count = 0;



		switch (info->query_hw_ip.type) {

		case AMDGPU_HW_IP_GFX:

			type = AMDGPU_IP_BLOCK_TYPE_GFX;

			type = AMD_IP_BLOCK_TYPE_GFX;

			break;

		case AMDGPU_HW_IP_COMPUTE:

			type = AMDGPU_IP_BLOCK_TYPE_GFX;

			type = AMD_IP_BLOCK_TYPE_GFX;

			break;

		case AMDGPU_HW_IP_DMA:

			type = AMDGPU_IP_BLOCK_TYPE_SDMA;

			type = AMD_IP_BLOCK_TYPE_SDMA;

			break;

		case AMDGPU_HW_IP_UVD:

			type = AMDGPU_IP_BLOCK_TYPE_UVD;

			type = AMD_IP_BLOCK_TYPE_UVD;

			break;

		case AMDGPU_HW_IP_VCE:

			type = AMDGPU_IP_BLOCK_TYPE_VCE;

			type = AMD_IP_BLOCK_TYPE_VCE;

			break;

		default:

			return -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

+1 −1
Original line number Diff line number Diff line
@@ -185,7 +185,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 
	}



	/* from uvd v5.0 HW addressing capacity increased to 64 bits */

	if (!amdgpu_ip_block_version_cmp(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 5, 0))

	if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))

		adev->uvd.address_64_bit = true;



	return 0;