Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5f68c275 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
Browse files

drm/i915: Unduplicate pre encoder enabling phy code 



The phy code in vlv_pre_enable_dp() and vlv_hdmi_pre_enable() is
exectly the same, so extract it to intel_dpio_phy.c.

Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarJim Bride <jim.bride@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461761065-21195-10-git-send-email-ander.conselvan.de.oliveira@intel.com
parent 6da2e616

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -3604,6 +3604,7 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, 
			      u32 demph_reg_value, u32 preemph_reg_value,

			      u32 uniqtranscale_reg_value, u32 tx3_demph);

void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);

void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);



int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);

int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);

drivers/gpu/drm/i915/intel_dp.c

+1 −23
Original line number Diff line number Diff line
@@ -2762,29 +2762,7 @@ static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) 


static void vlv_pre_enable_dp(struct intel_encoder *encoder)

{

	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);

	enum dpio_channel port = vlv_dport_to_channel(dport);

	int pipe = intel_crtc->pipe;

	u32 val;



	mutex_lock(&dev_priv->sb_lock);



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));

	val = 0;

	if (pipe)

		val |= (1<<21);

	else

		val &= ~(1<<21);

	val |= 0x001000c4;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);



	mutex_unlock(&dev_priv->sb_lock);

	vlv_phy_pre_encoder_enable(encoder);



	intel_enable_dp(encoder);

}

drivers/gpu/drm/i915/intel_dpio_phy.c

+30 −0
Original line number Diff line number Diff line
@@ -423,3 +423,33 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder) 
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);

	mutex_unlock(&dev_priv->sb_lock);

}



void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder)

{

	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);

	enum dpio_channel port = vlv_dport_to_channel(dport);

	int pipe = intel_crtc->pipe;

	u32 val;



	mutex_lock(&dev_priv->sb_lock);



	/* Enable clock channels for this port */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));

	val = 0;

	if (pipe)

		val |= (1<<21);

	else

		val &= ~(1<<21);

	val |= 0x001000c4;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);



	/* Program lane clock */

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);



	mutex_unlock(&dev_priv->sb_lock);

}

drivers/gpu/drm/i915/intel_hdmi.c

+1 −18
Original line number Diff line number Diff line
@@ -1594,25 +1594,8 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) 
	struct intel_crtc *intel_crtc =

		to_intel_crtc(encoder->base.crtc);

	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;

	enum dpio_channel port = vlv_dport_to_channel(dport);

	int pipe = intel_crtc->pipe;

	u32 val;



	/* Enable clock channels for this port */

	mutex_lock(&dev_priv->sb_lock);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));

	val = 0;

	if (pipe)

		val |= (1<<21);

	else

		val &= ~(1<<21);

	val |= 0x001000c4;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);



	/* Program lane clock */

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);

	mutex_unlock(&dev_priv->sb_lock);

	vlv_phy_pre_encoder_enable(encoder);



	/* HDMI 1.0V-2dB */

	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,