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Commit 5f0fbf9e authored by Nicolas Pitre's avatar Nicolas Pitre
Browse files

[ARM] fixmap support 



This is the minimum fixmap interface expected to be implemented by
architectures supporting highmem.

We have a second level page table already allocated and covering
0xfff00000-0xffffffff because the exception vector page is located
at 0xffff0000, and various cache tricks already use some entries above
0xffff0000.  Therefore the PTEs covering 0xfff00000-0xfffeffff are free
to be used.

However the XScale cache flushing code already uses virtual addresses
between 0xfffe0000 and 0xfffeffff.

So this reserves the 0xfff00000-0xfffdffff range for fixmap stuff.

The Documentation/arm/memory.txt information is updated accordingly,
including the information about the actual top of DMA memory mapping
region which didn't match the code.

Signed-off-by: default avatarNicolas Pitre <nico@marvell.com>
parent 1522ac3e

Documentation/arm/memory.txt

+8 −1
Original line number Diff line number Diff line
@@ -29,7 +29,14 @@ ffff0000 ffff0fff CPU vector page. 
				CPU supports vector relocation (control

				register V bit.)



ffc00000	fffeffff	DMA memory mapping region.  Memory returned

fffe0000	fffeffff	XScale cache flush area.  This is used

				in proc-xscale.S to flush the whole data

				cache.  Free for other usage on non-XScale.



fff00000	fffdffff	Fixmap mapping region.  Addresses provided

				by fix_to_virt() will be located here.



ffc00000	ffefffff	DMA memory mapping region.  Memory returned

				by the dma_alloc_xxx functions will be

				dynamically mapped here.

arch/arm/include/asm/fixmap.h

0 → 100644
+41 −0
Original line number Diff line number Diff line 
#ifndef _ASM_FIXMAP_H

#define _ASM_FIXMAP_H



/*

 * Nothing too fancy for now.

 *

 * On ARM we already have well known fixed virtual addresses imposed by

 * the architecture such as the vector page which is located at 0xffff0000,

 * therefore a second level page table is already allocated covering

 * 0xfff00000 upwards.

 *

 * The cache flushing code in proc-xscale.S uses the virtual area between

 * 0xfffe0000 and 0xfffeffff.

 */



#define FIXADDR_START		0xfff00000UL

#define FIXADDR_TOP		0xfffe0000UL

#define FIXADDR_SIZE		(FIXADDR_TOP - FIXADDR_START)



#define FIX_KMAP_BEGIN		0

#define FIX_KMAP_END		(FIXADDR_SIZE >> PAGE_SHIFT)



#define __fix_to_virt(x)	(FIXADDR_START + ((x) << PAGE_SHIFT))

#define __virt_to_fix(x)	(((x) - FIXADDR_START) >> PAGE_SHIFT)



extern void __this_fixmap_does_not_exist(void);



static inline unsigned long fix_to_virt(const unsigned int idx)

{

	if (idx >= FIX_KMAP_END)

		__this_fixmap_does_not_exist();

	return __fix_to_virt(idx);

}



static inline unsigned int virt_to_fix(const unsigned long vaddr)

{

	BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);

	return __virt_to_fix(vaddr);

}



#endif

arch/arm/mm/mm.h

+1 −2
Original line number Diff line number Diff line 
/* the upper-most page table pointer */



#ifdef CONFIG_MMU



/* the upper-most page table pointer */

extern pmd_t *top_pmd;



#define TOP_PTE(x)	pte_offset_kernel(top_pmd, x)