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Commit 5e49cea6 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: reindent Haswell register definitions 



It's the only part of the i915_reg.h file that looks totally wrongly
indented, so I assume my editor config is the correct one.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 602c43d3

drivers/gpu/drm/i915/i915_reg.h

+85 −99
Original line number Diff line number Diff line
@@ -4295,8 +4295,7 @@ 
#define PIPE_DDI_FUNC_CTL_B		0x61400

#define PIPE_DDI_FUNC_CTL_C		0x62400

#define PIPE_DDI_FUNC_CTL_EDP		0x6F400

#define DDI_FUNC_CTL(pipe) _PIPE(pipe, \

					PIPE_DDI_FUNC_CTL_A, \

#define DDI_FUNC_CTL(pipe) _PIPE(pipe, PIPE_DDI_FUNC_CTL_A, \

				       PIPE_DDI_FUNC_CTL_B)

#define  PIPE_DDI_FUNC_ENABLE		(1<<31)

/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
@@ -4323,9 +4322,7 @@ 
/* DisplayPort Transport Control */

#define DP_TP_CTL_A			0x64040

#define DP_TP_CTL_B			0x64140

#define DP_TP_CTL(port) _PORT(port, \

					DP_TP_CTL_A, \

					DP_TP_CTL_B)

#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)

#define  DP_TP_CTL_ENABLE			(1<<31)

#define  DP_TP_CTL_MODE_SST			(0<<27)

#define  DP_TP_CTL_MODE_MST			(1<<27)
@@ -4339,17 +4336,13 @@ 
/* DisplayPort Transport Status */

#define DP_TP_STATUS_A			0x64044

#define DP_TP_STATUS_B			0x64144

#define DP_TP_STATUS(port) _PORT(port, \

					DP_TP_STATUS_A, \

					DP_TP_STATUS_B)

#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)

#define  DP_TP_STATUS_AUTOTRAIN_DONE	(1<<12)



/* DDI Buffer Control */

#define DDI_BUF_CTL_A				0x64000

#define DDI_BUF_CTL_B				0x64100

#define DDI_BUF_CTL(port) _PORT(port, \

					DDI_BUF_CTL_A, \

					DDI_BUF_CTL_B)

#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)

#define  DDI_BUF_CTL_ENABLE			(1<<31)

#define  DDI_BUF_EMP_400MV_0DB_HSW		(0<<24)   /* Sel0 */

#define  DDI_BUF_EMP_400MV_3_5DB_HSW		(1<<24)   /* Sel1 */
@@ -4370,9 +4363,7 @@ 
/* DDI Buffer Translations */

#define DDI_BUF_TRANS_A				0x64E00

#define DDI_BUF_TRANS_B				0x64E60

#define DDI_BUF_TRANS(port) _PORT(port, \

					DDI_BUF_TRANS_A, \

					DDI_BUF_TRANS_B)

#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)



/* Sideband Interface (SBI) is programmed indirectly, via

 * SBI_ADDR, which contains the register offset; and SBI_DATA,
@@ -4430,9 +4421,7 @@ 
/* Port clock selection */

#define PORT_CLK_SEL_A			0x46100

#define PORT_CLK_SEL_B			0x46104

#define PORT_CLK_SEL(port) _PORT(port, \

					PORT_CLK_SEL_A, \

					PORT_CLK_SEL_B)

#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)

#define  PORT_CLK_SEL_LCPLL_2700	(0<<29)

#define  PORT_CLK_SEL_LCPLL_1350	(1<<29)

#define  PORT_CLK_SEL_LCPLL_810		(2<<29)
@@ -4443,9 +4432,7 @@ 
/* Pipe clock selection */

#define PIPE_CLK_SEL_A			0x46140

#define PIPE_CLK_SEL_B			0x46144

#define PIPE_CLK_SEL(pipe) _PIPE(pipe, \

					PIPE_CLK_SEL_A, \

					PIPE_CLK_SEL_B)

#define PIPE_CLK_SEL(pipe) _PIPE(pipe, PIPE_CLK_SEL_A, PIPE_CLK_SEL_B)

/* For each pipe, we need to select the corresponding port clock */

#define  PIPE_CLK_SEL_DISABLED		(0x0<<29)

#define  PIPE_CLK_SEL_PORT(x)		((x+1)<<29)
@@ -4460,8 +4447,7 @@ 
/* Pipe WM_LINETIME - watermark line time */

#define PIPE_WM_LINETIME_A		0x45270

#define PIPE_WM_LINETIME_B		0x45274

#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, \

					PIPE_WM_LINETIME_A, \

#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \

					   PIPE_WM_LINETIME_B)

#define   PIPE_WM_LINETIME_MASK			(0x1ff)

#define   PIPE_WM_LINETIME_TIME(x)		((x))