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Commit 5e40cd4d authored by Thor Thayer's avatar Thor Thayer Committed by Borislav Petkov
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Documentation: dt: socfpga: Add Arria10 SD-MMC EDAC binding 



Add the device tree bindings needed to support the Altera SD-MMC
FIFO buffers EDAC on the Arria10 chip.

Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1470153381-20517-2-git-send-email-tthayer@opensource.altera.com


Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent dc0a50a8

Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt

+19 −0
Original line number Original line Diff line number Diff line
@@ -122,6 +122,15 @@ Required Properties: 
- interrupts      : Should be single bit error interrupt, then double bit error

- interrupts      : Should be single bit error interrupt, then double bit error

	interrupt, in this order.

	interrupt, in this order.





SDMMC FIFO ECC

Required Properties:

- compatible      : Should be "altr,socfpga-sdmmc-ecc"

- reg             : Address and size for ECC block registers.

- altr,ecc-parent : phandle to parent SD/MMC node.

- interrupts      : Should be single bit error interrupt, then double bit error

	interrupt, in this order for port A, and then single bit error interrupt,

	then double bit error interrupt in this order for port B.



Example:

Example:





	eccmgr: eccmgr@ffd06000 {

	eccmgr: eccmgr@ffd06000 {
@@ -211,4 +220,14 @@ Example: 
			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,

			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,

				     <46 IRQ_TYPE_LEVEL_HIGH>;

				     <46 IRQ_TYPE_LEVEL_HIGH>;

		};

		};



		sdmmc-ecc@ff8c2c00 {

			compatible = "altr,socfpga-sdmmc-ecc";

			reg = <0xff8c2c00 0x400>;

			altr,ecc-parent = <&mmc>;

			interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,

				     <47 IRQ_TYPE_LEVEL_HIGH>,

				     <16 IRQ_TYPE_LEVEL_HIGH>,

				     <48 IRQ_TYPE_LEVEL_HIGH>;

		};

	};
 
	};