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Commit 5e1e9ba6 authored by Stuart Yoder's avatar Stuart Yoder Committed by Paul Mackerras
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[POWERPC] Add table of contents to booting-without-of.txt



Add table of contents.

Signed-off-by: default avatarStuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent e5c0b9ec
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           Booting the Linux/ppc kernel without Open Firmware
           --------------------------------------------------


(c) 2005 Benjamin Herrenschmidt <benh at kernel.crashing.org>,
    IBM Corp.
(c) 2005 Becky Bruce <becky.bruce at freescale.com>,
@@ -9,6 +8,62 @@
(c) 2006 MontaVista Software, Inc.
    Flash chip node definition

Table of Contents
=================

  I - Introduction
    1) Entry point for arch/powerpc
    2) Board support

  II - The DT block format
    1) Header
    2) Device tree generalities
    3) Device tree "structure" block
    4) Device tree "strings" block

  III - Required content of the device tree
    1) Note about cells and address representation
    2) Note about "compatible" properties
    3) Note about "name" properties
    4) Note about node and property names and character set
    5) Required nodes and properties
      a) The root node
      b) The /cpus node
      c) The /cpus/* nodes
      d) the /memory node(s)
      e) The /chosen node
      f) the /soc<SOCname> node

  IV - "dtc", the device tree compiler

  V - Recommendations for a bootloader

  VI - System-on-a-chip devices and nodes
    1) Defining child nodes of an SOC
    2) Representing devices without a current OF specification
      a) MDIO IO device
      c) PHY nodes
      b) Gianfar-compatible ethernet nodes
      d) Interrupt controllers
      e) I2C
      f) Freescale SOC USB controllers
      g) Freescale SOC SEC Security Engines
      h) Board Control and Status (BCSR)
      i) Freescale QUICC Engine module (QE)
      g) Flash chip nodes

  VII - Specifying interrupt information for devices
    1) interrupts property
    2) interrupt-parent property
    3) OpenPIC Interrupt Controllers
    4) ISA Interrupt Controllers

  Appendix A - Sample SOC node for MPC8540


Revision Information
====================

   May 18, 2005: Rev 0.1 - Initial draft, no chapter III yet.

   May 19, 2005: Rev 0.2 - Add chapter III and bits & pieces here or