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Commit 5e120f6e authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/fence: convert to exec engine, and improve channel sync 



Now have a somewhat simpler semaphore sync implementation for nv17:nv84,
and a switched to using semaphores as fences on nv84+ and making use of
the hardware's >= acquire operation.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent d375e7d5

drivers/gpu/drm/nouveau/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ 
             nv50_fb.o nvc0_fb.o \

             nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o nvc0_fifo.o \

             nve0_fifo.o \

             nv04_fence.o nv10_fence.o nv84_fence.o nvc0_fence.o \

             nv04_software.o nv50_software.o nvc0_software.o \

             nv04_graph.o nv10_graph.o nv20_graph.o \

             nv40_graph.o nv50_graph.o nvc0_graph.o nve0_graph.o \

drivers/gpu/drm/nouveau/nouveau_channel.c

+27 −22
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, 
		      struct drm_file *file_priv,

		      uint32_t vram_handle, uint32_t gart_handle)

{

	struct nouveau_exec_engine *fence = nv_engine(dev, NVOBJ_ENGINE_FENCE);

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;

	struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
@@ -157,8 +158,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, 
	}



	NV_DEBUG(dev, "initialising channel %d\n", chan->id);

	INIT_LIST_HEAD(&chan->fence.pending);

	spin_lock_init(&chan->fence.lock);



	/* setup channel's memory and vm */

	ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
@@ -211,7 +210,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, 


	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)

		OUT_RING  (chan, 0x00000000);

	FIRE_RING(chan);



	ret = nouveau_gpuobj_gr_new(chan, NvSw, nouveau_software_class(dev));

	if (ret) {
@@ -219,7 +217,21 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, 
		return ret;

	}



	ret = nouveau_fence_channel_init(chan);

	if (dev_priv->card_type < NV_C0) {

		ret = RING_SPACE(chan, 2);

		if (ret) {

			nouveau_channel_put(&chan);

			return ret;

		}



		BEGIN_NV04(chan, NvSubSw, NV01_SUBCHAN_OBJECT, 1);

		OUT_RING  (chan, NvSw);

		FIRE_RING (chan);

	}



	FIRE_RING(chan);



	ret = fence->context_new(chan, NVOBJ_ENGINE_FENCE);

	if (ret) {

		nouveau_channel_put(&chan);

		return ret;
@@ -291,12 +303,6 @@ nouveau_channel_put_unlocked(struct nouveau_channel **pchan) 
	/* give it chance to idle */

	nouveau_channel_idle(chan);



	/* ensure all outstanding fences are signaled.  they should be if the

	 * above attempts at idling were OK, but if we failed this'll tell TTM

	 * we're done with the buffers.

	 */

	nouveau_fence_channel_fini(chan);



	/* boot it off the hardware */

	pfifo->reassign(dev, false);
@@ -305,6 +311,9 @@ nouveau_channel_put_unlocked(struct nouveau_channel **pchan) 
	for (i = 0; i < NVOBJ_ENGINE_NR; i++) {

		if (chan->engctx[i])

			dev_priv->eng[i]->context_del(chan, i);

		/*XXX: clean this up later, order is important */

		if (i == NVOBJ_ENGINE_FENCE)

			pfifo->destroy_context(chan);

	}



	pfifo->reassign(dev, true);
@@ -367,9 +376,6 @@ nouveau_channel_idle(struct nouveau_channel *chan) 
	struct nouveau_fence *fence = NULL;

	int ret;



	nouveau_fence_update(chan);



	if (chan->fence.sequence != chan->fence.sequence_ack) {

	ret = nouveau_fence_new(chan, &fence);

	if (!ret) {

		ret = nouveau_fence_wait(fence, false, false);
@@ -379,7 +385,6 @@ nouveau_channel_idle(struct nouveau_channel *chan) 
	if (ret)

		NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);

}

}



/* cleans up all the fifos from file_priv */

void

drivers/gpu/drm/nouveau/nouveau_debugfs.c

+0 −2
Original line number Diff line number Diff line
@@ -67,8 +67,6 @@ nouveau_debugfs_channel_info(struct seq_file *m, void *data) 
			   nvchan_rd32(chan, 0x8c));

	}



	seq_printf(m, "last fence    : %d\n", chan->fence.sequence);

	seq_printf(m, "last signalled: %d\n", chan->fence.sequence_ack);

	return 0;

}

drivers/gpu/drm/nouveau/nouveau_display.c

+1 −1
Original line number Diff line number Diff line
@@ -461,7 +461,7 @@ nouveau_page_flip_emit(struct nouveau_channel *chan, 
		OUT_RING  (chan, 0x00000000);

	} else {

		BEGIN_NVC0(chan, 0, NV10_SUBCHAN_REF_CNT, 1);

		OUT_RING  (chan, ++chan->fence.sequence);

		OUT_RING  (chan, 0);

		BEGIN_IMC0(chan, 0, NVSW_SUBCHAN_PAGE_FLIP, 0x0000);

	}

	FIRE_RING (chan);

drivers/gpu/drm/nouveau/nouveau_drv.h

+2 −18
Original line number Diff line number Diff line
@@ -165,6 +165,7 @@ enum nouveau_flags { 
#define NVOBJ_ENGINE_PPP	NVOBJ_ENGINE_MPEG

#define NVOBJ_ENGINE_BSP	6

#define NVOBJ_ENGINE_VP		7

#define NVOBJ_ENGINE_FENCE	14

#define NVOBJ_ENGINE_DISPLAY	15

#define NVOBJ_ENGINE_NR		16
@@ -234,17 +235,6 @@ struct nouveau_channel { 
	uint32_t user_get_hi;

	uint32_t user_put;



	/* Fencing */

	struct {

		/* lock protects the pending list only */

		spinlock_t lock;

		struct list_head pending;

		uint32_t sequence;

		uint32_t sequence_ack;

		atomic_t last_sequence_irq;

		struct nouveau_vma vma;

	} fence;



	/* DMA push buffer */

	struct nouveau_gpuobj *pushbuf;

	struct nouveau_bo     *pushbuf_bo;
@@ -1443,13 +1433,6 @@ extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 
			       struct nouveau_vma *);

extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);



/* nouveau_fence.c */

int  nouveau_fence_init(struct drm_device *);

void nouveau_fence_fini(struct drm_device *);

int  nouveau_fence_channel_init(struct nouveau_channel *);

void nouveau_fence_channel_fini(struct nouveau_channel *);

void nouveau_fence_work(struct nouveau_fence *fence,

			void (*work)(void *priv, bool signalled), void *priv);

/* nouveau_gem.c */

extern int nouveau_gem_new(struct drm_device *, int size, int align,

			   uint32_t domain, uint32_t tile_mode,
@@ -1746,6 +1729,7 @@ nv44_graph_class(struct drm_device *dev) 
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL                 0x00000001

#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG                    0x00000002

#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL                0x00000004

#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD                         0x00001000

#define NV84_SUBCHAN_NOTIFY_INTR                                     0x00000020

#define NV84_SUBCHAN_WRCACHE_FLUSH                                   0x00000024

#define NV10_SUBCHAN_REF_CNT                                         0x00000050