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Commit 5c6201e6 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Stephen Boyd
Browse files

clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCs 



I made a mistake as for naming for this block.  The MIO block is not
implemented for these 3 SoCs in the first place.  The current naming
will be a trouble if an SoC with both MIO and SD-ctrl blocks appear
in the future.

This driver has just been merged in the previous merge window.
Rename it before the release.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 7d36b9c1

Documentation/devicetree/bindings/clock/uniphier-clock.txt

+8 −8
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ Example: 
		reg = <0x61840000 0x4000>;



		clock {

			compatible = "socionext,uniphier-ld20-clock";

			compatible = "socionext,uniphier-ld11-clock";

			#clock-cells = <1>;

		};
@@ -43,8 +43,8 @@ Provided clocks: 
21: USB3 ch1 PHY1





Media I/O (MIO) clock

---------------------

Media I/O (MIO) clock, SD clock

-------------------------------



Required properties:

- compatible: should be one of the following:
@@ -52,10 +52,10 @@ Required properties: 
    "socionext,uniphier-ld4-mio-clock"  - for LD4 SoC.

    "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.

    "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.

    "socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.

    "socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.

    "socionext,uniphier-pro5-sd-clock"  - for Pro5 SoC.

    "socionext,uniphier-pxs2-sd-clock"  - for PXs2/LD6b SoC.

    "socionext,uniphier-ld11-mio-clock" - for LD11 SoC.

    "socionext,uniphier-ld20-mio-clock" - for LD20 SoC.

    "socionext,uniphier-ld20-sd-clock"  - for LD20 SoC.

- #clock-cells: should be 1.



Example:
@@ -66,7 +66,7 @@ Example: 
		reg = <0x59810000 0x800>;



		clock {

			compatible = "socionext,uniphier-ld20-mio-clock";

			compatible = "socionext,uniphier-ld11-mio-clock";

			#clock-cells = <1>;

		};
@@ -112,7 +112,7 @@ Example: 
		reg = <0x59820000 0x200>;



		clock {

			compatible = "socionext,uniphier-ld20-peri-clock";

			compatible = "socionext,uniphier-ld11-peri-clock";

			#clock-cells = <1>;

		};

drivers/clk/uniphier/clk-uniphier-core.c

+7 −7
Original line number Diff line number Diff line
@@ -142,7 +142,7 @@ static const struct of_device_id uniphier_clk_match[] = { 
		.compatible = "socionext,uniphier-ld20-clock",

		.data = uniphier_ld20_sys_clk_data,

	},

	/* Media I/O clock */

	/* Media I/O clock, SD clock */

	{

		.compatible = "socionext,uniphier-sld3-mio-clock",

		.data = uniphier_sld3_mio_clk_data,
@@ -160,20 +160,20 @@ static const struct of_device_id uniphier_clk_match[] = { 
		.data = uniphier_sld3_mio_clk_data,

	},

	{

		.compatible = "socionext,uniphier-pro5-mio-clock",

		.data = uniphier_pro5_mio_clk_data,

		.compatible = "socionext,uniphier-pro5-sd-clock",

		.data = uniphier_pro5_sd_clk_data,

	},

	{

		.compatible = "socionext,uniphier-pxs2-mio-clock",

		.data = uniphier_pro5_mio_clk_data,

		.compatible = "socionext,uniphier-pxs2-sd-clock",

		.data = uniphier_pro5_sd_clk_data,

	},

	{

		.compatible = "socionext,uniphier-ld11-mio-clock",

		.data = uniphier_sld3_mio_clk_data,

	},

	{

		.compatible = "socionext,uniphier-ld20-mio-clock",

		.data = uniphier_pro5_mio_clk_data,

		.compatible = "socionext,uniphier-ld20-sd-clock",

		.data = uniphier_pro5_sd_clk_data,

	},

	/* Peripheral clock */

	{

drivers/clk/uniphier/clk-uniphier-mio.c

+1 −1
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ const struct uniphier_clk_data uniphier_sld3_mio_clk_data[] = { 
	{ /* sentinel */ }

};



const struct uniphier_clk_data uniphier_pro5_mio_clk_data[] = {

const struct uniphier_clk_data uniphier_pro5_sd_clk_data[] = {

	UNIPHIER_MIO_CLK_SD_FIXED,

	UNIPHIER_MIO_CLK_SD(0, 0),

	UNIPHIER_MIO_CLK_SD(1, 1),

drivers/clk/uniphier/clk-uniphier.h

+1 −1
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[]; 
extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];

extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];

extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];

extern const struct uniphier_clk_data uniphier_pro5_mio_clk_data[];

extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];

extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];

extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];