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Commit 5b7abc6f authored by H. Peter Anvin's avatar H. Peter Anvin Committed by Linus Torvalds
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[PATCH] CPUID bug and inconsistency fix 



The recent support for K8 multicore was misported from x86-64 to i386, due
to an unnecessary inconsistency between the CPUID code.  Sure, there is are
no x86-64 VIA chips yet, but it should happen eventually.

This patch fixes the i386 bug as well as makes x86-64 match i386 in the
handing of the CPUID array.

Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent a6954ba2

arch/x86_64/kernel/setup.c

+8 −2
Original line number Diff line number Diff line
@@ -977,7 +977,7 @@ void __init identify_cpu(struct cpuinfo_x86 *c) 
	if ((xlvl & 0xffff0000) == 0x80000000) {

		if (xlvl >= 0x80000001) {

			c->x86_capability[1] = cpuid_edx(0x80000001);

			c->x86_capability[5] = cpuid_ecx(0x80000001);

			c->x86_capability[6] = cpuid_ecx(0x80000001);

		}

		if (xlvl >= 0x80000004)

			get_model_name(c); /* Default name */
@@ -1100,11 +1100,17 @@ static int show_cpuinfo(struct seq_file *m, void *v) 
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,



		/* VIA/Cyrix/Centaur-defined */

		NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,



		/* AMD-defined (#2) */

		"lahf_lm", "cmp_legacy", NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

	};

	static char *x86_power_flags[] = { 

		"ts",	/* temperature sensor */

include/asm-i386/cpufeature.h

+2 −2
Original line number Diff line number Diff line
@@ -87,8 +87,8 @@ 
#define X86_FEATURE_XCRYPT_EN	(5*32+ 7) /* on-CPU crypto enabled */



/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */

#define X86_FEATURE_LAHF_LM	(5*32+ 0) /* LAHF/SAHF in long mode */

#define X86_FEATURE_CMP_LEGACY	(5*32+ 1) /* If yes HyperThreading not valid */

#define X86_FEATURE_LAHF_LM	(6*32+ 0) /* LAHF/SAHF in long mode */

#define X86_FEATURE_CMP_LEGACY	(6*32+ 1) /* If yes HyperThreading not valid */



#define cpu_has(c, bit)		test_bit(bit, (c)->x86_capability)

#define boot_cpu_has(bit)	test_bit(bit, boot_cpu_data.x86_capability)

include/asm-x86_64/cpufeature.h

+10 −4
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 
#ifndef __ASM_X8664_CPUFEATURE_H

#define __ASM_X8664_CPUFEATURE_H



#define NCAPINTS	6

#define NCAPINTS	7	/* N 32-bit words worth of info */



/* Intel-defined CPU features, CPUID level 0x00000001, word 0 */

#define X86_FEATURE_FPU		(0*32+ 0) /* Onboard FPU */
@@ -74,9 +74,15 @@ 
#define X86_FEATURE_CX16	(4*32+13) /* CMPXCHG16B */

#define X86_FEATURE_XTPR	(4*32+14) /* Send Task Priority Messages */



/* More extended AMD flags: CPUID level 0x80000001, ecx, word 5 */

#define X86_FEATURE_LAHF_LM	(5*32+ 0) /* LAHF/SAHF in long mode */

#define X86_FEATURE_CMP_LEGACY	(5*32+ 1) /* If yes HyperThreading not valid */

/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */

#define X86_FEATURE_XSTORE	(5*32+ 2) /* on-CPU RNG present (xstore insn) */

#define X86_FEATURE_XSTORE_EN	(5*32+ 3) /* on-CPU RNG enabled */

#define X86_FEATURE_XCRYPT	(5*32+ 6) /* on-CPU crypto (xcrypt insn) */

#define X86_FEATURE_XCRYPT_EN	(5*32+ 7) /* on-CPU crypto enabled */



/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */

#define X86_FEATURE_LAHF_LM	(6*32+ 0) /* LAHF/SAHF in long mode */

#define X86_FEATURE_CMP_LEGACY	(6*32+ 1) /* If yes HyperThreading not valid */



#define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)

#define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)