Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5ad73d07 authored by Linus Walleij's avatar Linus Walleij Committed by Russell King
Browse files

ARM: 5665/1: U300 syscon register updates 



This adds in a few new register and defines for improved padmux
support and some figures that were plain wrong on the targeted
U300 platforms.

Signed-off-by: default avatarLinus Walleij <linus.walleij@stericsson.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 28d0325c

arch/arm/mach-u300/include/mach/syscon.h

+113 −7
Original line number Diff line number Diff line
@@ -240,8 +240,13 @@ 
#define U300_SYSCON_PMC1LR_CDI_MASK				(0xC000)

#define U300_SYSCON_PMC1LR_CDI_CDI				(0x0000)

#define U300_SYSCON_PMC1LR_CDI_EMIF				(0x4000)

#ifdef CONFIG_MACH_U300_BS335

#define U300_SYSCON_PMC1LR_CDI_CDI2				(0x8000)

#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO			(0xC000)

#elif CONFIG_MACH_U300_BS365

#define U300_SYSCON_PMC1LR_CDI_GPIO				(0x8000)

#define U300_SYSCON_PMC1LR_CDI_WCDMA				(0xC000)

#endif

#define U300_SYSCON_PMC1LR_PDI_MASK				(0x3000)

#define U300_SYSCON_PMC1LR_PDI_PDI				(0x0000)

#define U300_SYSCON_PMC1LR_PDI_EGG				(0x1000)
@@ -345,19 +350,69 @@ 
#define U300_SYSCON_MMCR_MASK					(0x0003)

#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE			(0x0002)

#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE			(0x0001)



/* Pull up/down control (R/W) */

#define U300_SYSCON_PUCR					(0x104)

#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE		(0x0200)

#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE		(0x0100)

#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE			(0x0080)

#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE			(0x0040)

#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK			(0x003F)

/* Padmux 2 control */

#define U300_SYSCON_PMC2R					(0x100)

#define U300_SYSCON_PMC2R_APP_MISC_0_MASK			(0x00C0)

#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO			(0x0000)

#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM			(0x0040)

#define U300_SYSCON_PMC2R_APP_MISC_0_MMC			(0x0080)

#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2			(0x00C0)

#define U300_SYSCON_PMC2R_APP_MISC_1_MASK			(0x0300)

#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO			(0x0000)

#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM			(0x0100)

#define U300_SYSCON_PMC2R_APP_MISC_1_MMC			(0x0200)

#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2			(0x0300)

#define U300_SYSCON_PMC2R_APP_MISC_2_MASK			(0x0C00)

#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO			(0x0000)

#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM			(0x0400)

#define U300_SYSCON_PMC2R_APP_MISC_2_MMC			(0x0800)

#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2			(0x0C00)

#define U300_SYSCON_PMC2R_APP_MISC_3_MASK			(0x3000)

#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO			(0x0000)

#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM			(0x1000)

#define U300_SYSCON_PMC2R_APP_MISC_3_MMC			(0x2000)

#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2			(0x3000)

#define U300_SYSCON_PMC2R_APP_MISC_4_MASK			(0xC000)

#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO			(0x0000)

#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM			(0x4000)

#define U300_SYSCON_PMC2R_APP_MISC_4_MMC			(0x8000)

#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO			(0xC000)

/* TODO: More SYSCON registers missing */

#define U300_SYSCON_PMC3R					(0x10c)

#define U300_SYSCON_PMC3R_APP_MISC_11_MASK			(0xc000)

#define U300_SYSCON_PMC3R_APP_MISC_11_SPI			(0x4000)

#define U300_SYSCON_PMC3R_APP_MISC_10_MASK			(0x3000)

#define U300_SYSCON_PMC3R_APP_MISC_10_SPI			(0x1000)

/* TODO: Missing other configs, I just added the SPI stuff */



/* TODO: Missing other configs */

#define U300_SYSCON_PMC4R					(0x168)

#define U300_SYSCON_PMC4R_APP_MISC_12_MASK			(0x0003)

#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO			(0x0000)

#define U300_SYSCON_PMC4R_APP_MISC_13_MASK			(0x000C)

#define U300_SYSCON_PMC4R_APP_MISC_13_CDI			(0x0000)

#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA			(0x0004)

#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2			(0x0008)

#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO			(0x000C)

#define U300_SYSCON_PMC4R_APP_MISC_14_MASK			(0x0030)

#define U300_SYSCON_PMC4R_APP_MISC_14_CDI			(0x0000)

#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA			(0x0010)

#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2			(0x0020)

#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO			(0x0030)

#define U300_SYSCON_PMC4R_APP_MISC_16_MASK			(0x0300)

#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13		(0x0000)

#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS		(0x0100)

#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N	(0x0200)

/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */

#define U300_SYSCON_S0CCR					(0x120)

#define U300_SYSCON_S0CCR_FIELD_MASK				(0x43FF)

#define U300_SYSCON_S0CCR_CLOCK_REQ				(0x4000)

#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR			(0x2000)

#define U300_SYSCON_S0CCR_CLOCK_INV				(0x0200)

#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK			(0x01E0)

#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK			(0x001E)
@@ -375,6 +430,7 @@ 
#define U300_SYSCON_S1CCR					(0x124)

#define U300_SYSCON_S1CCR_FIELD_MASK				(0x43FF)

#define U300_SYSCON_S1CCR_CLOCK_REQ				(0x4000)

#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR			(0x2000)

#define U300_SYSCON_S1CCR_CLOCK_INV				(0x0200)

#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK			(0x01E0)

#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK			(0x001E)
@@ -393,6 +449,7 @@ 
#define U300_SYSCON_S2CCR_FIELD_MASK				(0xC3FF)

#define U300_SYSCON_S2CCR_CLK_STEAL				(0x8000)

#define U300_SYSCON_S2CCR_CLOCK_REQ				(0x4000)

#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR			(0x2000)

#define U300_SYSCON_S2CCR_CLOCK_INV				(0x0200)

#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK			(0x01E0)

#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK			(0x001E)
@@ -425,6 +482,44 @@ 
#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM			(0x000C)

#define U300_SYSCON_MCR_PM1G_MODE_ENABLE			(0x0002)

#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE			(0x0001)

/* SC_PLL_IRQ_CONTROL 16bit (R/W) */

#define U300_SYSCON_PICR					(0x0130)

#define U300_SYSCON_PICR_MASK					(0x00FF)

#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE		(0x0080)

#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE		(0x0040)

#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE		(0x0020)

#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE		(0x0010)

#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE		(0x0008)

#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE		(0x0004)

#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE		(0x0002)

#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE		(0x0001)

/* SC_PLL_IRQ_STATUS 16 bit (R/-) */

#define U300_SYSCON_PISR					(0x0134)

#define U300_SYSCON_PISR_MASK					(0x000F)

#define U300_SYSCON_PISR_PLL13_UNLOCK_IND			(0x0008)

#define U300_SYSCON_PISR_PLL13_LOCK_IND				(0x0004)

#define U300_SYSCON_PISR_PLL208_UNLOCK_IND			(0x0002)

#define U300_SYSCON_PISR_PLL208_LOCK_IND			(0x0001)

/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */

#define U300_SYSCON_PICLR					(0x0138)

#define U300_SYSCON_PICLR_MASK					(0x000F)

#define U300_SYSCON_PICLR_RWMASK				(0x0000)

#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC			(0x0008)

#define U300_SYSCON_PICLR_PLL13_LOCK_SC				(0x0004)

#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC			(0x0002)

#define U300_SYSCON_PICLR_PLL208_LOCK_SC			(0x0001)

/* CAMIF_CONTROL 16 bit (-/W) */

#define U300_SYSCON_CICR					(0x013C)

#define U300_SYSCON_CICR_MASK					(0x0FFF)

#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK		(0x0F00)

#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1		(0x0C00)

#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0		(0x0300)

#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK		(0x00F0)

#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1		(0x00C0)

#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0		(0x0030)

#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK		(0x000F)

#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1		(0x000C)

#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0		(0x0003)

/* Clock activity observability register 0 */

#define U300_SYSCON_C0OAR					(0x140)

#define U300_SYSCON_C0OAR_MASK					(0xFFFF)
@@ -513,7 +608,7 @@ 
/**

 * CPU medium frequency in MHz

 */

#define SYSCON_CPU_CLOCK_MEDIUM  104

#define SYSCON_CPU_CLOCK_MEDIUM   52

/**

 * CPU low frequency in MHz

 */
@@ -527,7 +622,7 @@ 
/**

 * EMIF medium frequency in MHz

 */

#define SYSCON_EMIF_CLOCK_MEDIUM 104

#define SYSCON_EMIF_CLOCK_MEDIUM  52

/**

 * EMIF low frequency in MHz

 */
@@ -541,7 +636,7 @@ 
/**

 * AHB medium frequency in MHz

 */

#define SYSCON_AHB_CLOCK_MEDIUM   52

#define SYSCON_AHB_CLOCK_MEDIUM   26

/**

 * AHB low frequency in MHz

 */
@@ -553,6 +648,15 @@ enum syscon_busmaster { 
  SYSCON_BM_VIDEO_ENC

};



/* Selectr a resistor or a set of resistors */

enum syscon_pull_up_down {

  SYSCON_PU_KEY_IN_EN,

  SYSCON_PU_EMIF_1_8_BIT_EN,

  SYSCON_PU_EMIF_1_16_BIT_EN,

  SYSCON_PU_EMIF_1_NFIF_READY_EN,

  SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN,

};



/*

 * Note that this array must match the order of the array "clk_reg"

 * in syscon.c
@@ -575,6 +679,7 @@ enum syscon_clk { 
  SYSCON_CLKCONTROL_SPI,

  SYSCON_CLKCONTROL_I2S0_CORE,

  SYSCON_CLKCONTROL_I2S1_CORE,

  SYSCON_CLKCONTROL_UART1,

  SYSCON_CLKCONTROL_AAIF,

  SYSCON_CLKCONTROL_AHB,

  SYSCON_CLKCONTROL_APEX,
@@ -604,7 +709,8 @@ enum syscon_sysclk_mode { 


enum syscon_sysclk_req {

  SYSCON_SYSCLKREQ_DISABLED,

  SYSCON_SYSCLKREQ_ACTIVE_LOW

  SYSCON_SYSCLKREQ_ACTIVE_LOW,

  SYSCON_SYSCLKREQ_MONITOR

};



enum syscon_clk_mode {