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Commit 5a783cbc authored by Will Deacon's avatar Will Deacon Committed by Russell King
Browse files

ARM: 7478/1: errata: extend workaround for erratum #720789 



Commit cdf357f1 ("ARM: 6299/1: errata: TLBIASIDIS and TLBIMVAIS
operations can broadcast a faulty ASID") replaced by-ASID TLB flushing
operations with all-ASID variants to workaround A9 erratum #720789.

This patch extends the workaround to include the tlb_range operations,
which were overlooked by the original patch.

Cc: <stable@vger.kernel.org>
Tested-by: default avatarSteve Capper <steve.capper@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 24b35521

arch/arm/mm/tlb-v7.S

+12 −0
Original line number Original line Diff line number Diff line
@@ -38,11 +38,19 @@ ENTRY(v7wbi_flush_user_tlb_range) 
	dsb

	dsb

	mov	r0, r0, lsr #PAGE_SHIFT		@ align address

	mov	r0, r0, lsr #PAGE_SHIFT		@ align address

	mov	r1, r1, lsr #PAGE_SHIFT

	mov	r1, r1, lsr #PAGE_SHIFT

#ifdef CONFIG_ARM_ERRATA_720789

	mov	r3, #0

#else

	asid	r3, r3				@ mask ASID

	asid	r3, r3				@ mask ASID

#endif

	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA

	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA

	mov	r1, r1, lsl #PAGE_SHIFT

	mov	r1, r1, lsl #PAGE_SHIFT

1:

1:

#ifdef CONFIG_ARM_ERRATA_720789

	ALT_SMP(mcr	p15, 0, r0, c8, c3, 3)	@ TLB invalidate U MVA all ASID (shareable)

#else

	ALT_SMP(mcr	p15, 0, r0, c8, c3, 1)	@ TLB invalidate U MVA (shareable)

	ALT_SMP(mcr	p15, 0, r0, c8, c3, 1)	@ TLB invalidate U MVA (shareable)

#endif

	ALT_UP(mcr	p15, 0, r0, c8, c7, 1)	@ TLB invalidate U MVA

	ALT_UP(mcr	p15, 0, r0, c8, c7, 1)	@ TLB invalidate U MVA





	add	r0, r0, #PAGE_SZ

	add	r0, r0, #PAGE_SZ
@@ -67,7 +75,11 @@ ENTRY(v7wbi_flush_kern_tlb_range) 
	mov	r0, r0, lsl #PAGE_SHIFT

	mov	r0, r0, lsl #PAGE_SHIFT

	mov	r1, r1, lsl #PAGE_SHIFT

	mov	r1, r1, lsl #PAGE_SHIFT

1:

1:

#ifdef CONFIG_ARM_ERRATA_720789

	ALT_SMP(mcr	p15, 0, r0, c8, c3, 3)	@ TLB invalidate U MVA all ASID (shareable)

#else

	ALT_SMP(mcr	p15, 0, r0, c8, c3, 1)	@ TLB invalidate U MVA (shareable)

	ALT_SMP(mcr	p15, 0, r0, c8, c3, 1)	@ TLB invalidate U MVA (shareable)

#endif

	ALT_UP(mcr	p15, 0, r0, c8, c7, 1)	@ TLB invalidate U MVA

	ALT_UP(mcr	p15, 0, r0, c8, c7, 1)	@ TLB invalidate U MVA

	add	r0, r0, #PAGE_SZ

	add	r0, r0, #PAGE_SZ

	cmp	r0, r1

	cmp	r0, r1