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Commit 59f2d0fc authored by Zhenyu Wang's avatar Zhenyu Wang Committed by Eric Anholt
Browse files

drm/i915: Fix check with IS_GEN6 



IS_GEN6 missed to include SandyBridge mobile chip, which failed in
i915_probe_agp() for memory config detection. Fix it with a device
info flag.

Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 76e47c30

drivers/gpu/drm/i915/i915_drv.c

+2 −2
Original line number Diff line number Diff line
@@ -139,12 +139,12 @@ const static struct intel_device_info intel_ironlake_m_info = { 


const static struct intel_device_info intel_sandybridge_d_info = {

	.is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,

	.has_hotplug = 1,

	.has_hotplug = 1, .is_gen6 = 1,

};



const static struct intel_device_info intel_sandybridge_m_info = {

	.is_i965g = 1, .is_mobile = 1, .is_i9xx = 1, .need_gfx_hws = 1,

	.has_hotplug = 1,

	.has_hotplug = 1, .is_gen6 = 1,

};



const static struct pci_device_id pciidlist[] = {

drivers/gpu/drm/i915/i915_drv.h

+2 −2
Original line number Diff line number Diff line
@@ -205,6 +205,7 @@ struct intel_device_info { 
	u8 is_g4x : 1;

	u8 is_pineview : 1;

	u8 is_ironlake : 1;

	u8 is_gen6 : 1;

	u8 has_fbc : 1;

	u8 has_rc6 : 1;

	u8 has_pipe_cxsr : 1;
@@ -1084,6 +1085,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
#define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)

#define IS_IRONLAKE(dev)	(INTEL_INFO(dev)->is_ironlake)

#define IS_I9XX(dev)		(INTEL_INFO(dev)->is_i9xx)

#define IS_GEN6(dev)		(INTEL_INFO(dev)->is_gen6)

#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)



#define IS_GEN3(dev)	(IS_I915G(dev) ||			\
@@ -1107,8 +1109,6 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 


#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)



#define IS_GEN6(dev)	((dev)->pci_device == 0x0102)



/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte

 * rows, which changed the alignment requirements and fence programming.

 */