Loading drivers/gpu/drm/radeon/radeon_drv.c +1 −1 Original line number Diff line number Diff line Loading @@ -48,7 +48,7 @@ * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query */ #define KMS_DRIVER_MAJOR 2 #define KMS_DRIVER_MINOR 8 Loading drivers/gpu/drm/radeon/radeon_kms.c +4 −0 Original line number Diff line number Diff line Loading @@ -201,6 +201,10 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) } radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value); break; case RADEON_INFO_CLOCK_CRYSTAL_FREQ: /* return clock value in KHz */ value = rdev->clock.spll.reference_freq * 10; break; default: DRM_DEBUG_KMS("Invalid request %d\n", info->request); return -EINVAL; Loading include/drm/radeon_drm.h +1 −0 Original line number Diff line number Diff line Loading @@ -907,6 +907,7 @@ struct drm_radeon_cs { #define RADEON_INFO_TILING_CONFIG 0x06 #define RADEON_INFO_WANT_HYPERZ 0x07 #define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ struct drm_radeon_info { uint32_t request; Loading Loading
drivers/gpu/drm/radeon/radeon_drv.c +1 −1 Original line number Diff line number Diff line Loading @@ -48,7 +48,7 @@ * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query */ #define KMS_DRIVER_MAJOR 2 #define KMS_DRIVER_MINOR 8 Loading
drivers/gpu/drm/radeon/radeon_kms.c +4 −0 Original line number Diff line number Diff line Loading @@ -201,6 +201,10 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) } radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value); break; case RADEON_INFO_CLOCK_CRYSTAL_FREQ: /* return clock value in KHz */ value = rdev->clock.spll.reference_freq * 10; break; default: DRM_DEBUG_KMS("Invalid request %d\n", info->request); return -EINVAL; Loading
include/drm/radeon_drm.h +1 −0 Original line number Diff line number Diff line Loading @@ -907,6 +907,7 @@ struct drm_radeon_cs { #define RADEON_INFO_TILING_CONFIG 0x06 #define RADEON_INFO_WANT_HYPERZ 0x07 #define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ struct drm_radeon_info { uint32_t request; Loading