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Commit 5704195c authored by Akash Goel's avatar Akash Goel Committed by Daniel Vetter
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drm/i915/skl: Updated the gen6_set_rps function 



On SKL, the frequency is programmed differently in RPNSWREQ (A008)
register (from bits 23 to 31, compared to bits 24 to 31). So updated
the gen6_set_rps function, as per this change.

Signed-off-by: default avatarAkash Goel <akash.goel@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent cee991cb

drivers/gpu/drm/i915/intel_pm.c

+4 −1
Original line number Diff line number Diff line
@@ -3947,7 +3947,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) 
	if (val != dev_priv->rps.cur_freq) {

		gen6_set_rps_thresholds(dev_priv, val);



		if (IS_HASWELL(dev) || IS_BROADWELL(dev))

		if (IS_GEN9(dev))

			I915_WRITE(GEN6_RPNSWREQ,

				   GEN9_FREQUENCY(val));

		else if (IS_HASWELL(dev) || IS_BROADWELL(dev))

			I915_WRITE(GEN6_RPNSWREQ,

				   HSW_FREQUENCY(val));

		else