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Commit 55b6019a authored by Kevin Hilman's avatar Kevin Hilman
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OMAP: GPIO: clear/restore level/edge detect settings on mask/unmask 



If IRQ triggering is enabled, it can trigger a pending interrupt
even for masked interrupts.  Any pending GPIO interrupts can
prevent the powerdomain from hitting retention.

Problem found, reported and additional review and testing by Chunquiu
Wang.

Tested-by: default avatarChunquiu Wang <cqwang@motorola.com>
Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
parent 6c5f8039

arch/arm/plat-omap/gpio.c

+6 −0
Original line number Diff line number Diff line
@@ -1189,6 +1189,7 @@ static void gpio_mask_irq(unsigned int irq) 
	struct gpio_bank *bank = get_irq_chip_data(irq);



	_set_gpio_irqenable(bank, gpio, 0);

	_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);

}



static void gpio_unmask_irq(unsigned int irq)
@@ -1196,6 +1197,11 @@ static void gpio_unmask_irq(unsigned int irq) 
	unsigned int gpio = irq - IH_GPIO_BASE;

	struct gpio_bank *bank = get_irq_chip_data(irq);

	unsigned int irq_mask = 1 << get_gpio_index(gpio);

	struct irq_desc *desc = irq_to_desc(irq);

	u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;



	if (trigger)

		_set_gpio_triggering(bank, get_gpio_index(gpio), trigger);



	/* For level-triggered GPIOs, the clearing must be done after

	 * the HW source is cleared, thus after the handler has run */