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Commit 5557ae0e authored by Paul Mackerras's avatar Paul Mackerras Committed by Alexander Graf
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KVM: PPC: Book3S HV: Implement architecture compatibility modes for POWER8 



This allows us to select architecture 2.05 (POWER6) or 2.06 (POWER7)
compatibility modes on a POWER8 processor.  (Note that transactional
memory is disabled for usermode if either or both of the PCR_TM_DIS
and PCR_ARCH_206 bits are set.)

Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
parent bd3048b8

arch/powerpc/include/asm/reg.h

+2 −0
Original line number Diff line number Diff line
@@ -329,6 +329,8 @@ 
#define SPRN_PCR	0x152	/* Processor compatibility register */

#define   PCR_VEC_DIS	(1ul << (63-0))	/* Vec. disable (bit NA since POWER8) */

#define   PCR_VSX_DIS	(1ul << (63-1))	/* VSX disable (bit NA since POWER8) */

#define   PCR_TM_DIS	(1ul << (63-2))	/* Trans. memory disable (POWER8) */

#define   PCR_ARCH_206	0x4		/* Architecture 2.06 */

#define   PCR_ARCH_205	0x2		/* Architecture 2.05 */

#define	SPRN_HEIR	0x153	/* Hypervisor Emulated Instruction Register */

#define SPRN_TLBINDEXR	0x154	/* P7 TLB control register */

arch/powerpc/kvm/book3s_hv.c

+15 −1
Original line number Diff line number Diff line
@@ -184,14 +184,28 @@ int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat) 


		switch (arch_compat) {

		case PVR_ARCH_205:

			pcr = PCR_ARCH_205;

			/*

			 * If an arch bit is set in PCR, all the defined

			 * higher-order arch bits also have to be set.

			 */

			pcr = PCR_ARCH_206 | PCR_ARCH_205;

			break;

		case PVR_ARCH_206:

		case PVR_ARCH_206p:

			pcr = PCR_ARCH_206;

			break;

		case PVR_ARCH_207:

			break;

		default:

			return -EINVAL;

		}



		if (!cpu_has_feature(CPU_FTR_ARCH_207S)) {

			/* POWER7 can't emulate POWER8 */

			if (!(pcr & PCR_ARCH_206))

				return -EINVAL;

			pcr &= ~PCR_ARCH_206;

		}

	}



	spin_lock(&vc->lock);