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Commit 55249e9e authored by Michael Hennerich's avatar Michael Hennerich Committed by Bryan Wu
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Blackfin arch: For compatibility reasons change IRQ_XXX_ERR into IRQ_XXX_ERROR... 


Blackfin arch: For compatibility reasons change IRQ_XXX_ERR into IRQ_XXX_ERROR like on any other supported Blackfin derivative

Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
parent 02f13f9d

include/asm-blackfin/mach-bf548/irq.h

+308 −281
Original line number Diff line number Diff line
@@ -66,12 +66,12 @@ Events (highest priority) EMU 0 
#define BFIN_IRQ(x)		((x) + 7)



#define IRQ_PLL_WAKEUP		BFIN_IRQ(0)	/* PLL Wakeup Interrupt */

#define IRQ_DMAC0_ERR	BFIN_IRQ(1)	/* DMAC0 Status Interrupt */

#define IRQ_EPPI0_ERR	BFIN_IRQ(2)	/* EPPI0 Error Interrupt */

#define IRQ_SPORT0_ERR	BFIN_IRQ(3)	/* SPORT0 Error Interrupt */

#define IRQ_SPORT1_ERR	BFIN_IRQ(4)	/* SPORT1 Error Interrupt */

#define IRQ_SPI0_ERR	BFIN_IRQ(5)	/* SPI0 Status(Error) Interrupt */

#define IRQ_UART0_ERR	BFIN_IRQ(6)	/* UART0 Status(Error) Interrupt */

#define IRQ_DMAC0_ERROR		BFIN_IRQ(1)	/* DMAC0 Status Interrupt */

#define IRQ_EPPI0_ERROR		BFIN_IRQ(2)	/* EPPI0 Error Interrupt */

#define IRQ_SPORT0_ERROR	BFIN_IRQ(3)	/* SPORT0 Error Interrupt */

#define IRQ_SPORT1_ERROR	BFIN_IRQ(4)	/* SPORT1 Error Interrupt */

#define IRQ_SPI0_ERROR		BFIN_IRQ(5)	/* SPI0 Status(Error) Interrupt */

#define IRQ_UART0_ERROR		BFIN_IRQ(6)	/* UART0 Status(Error) Interrupt */

#define IRQ_RTC			BFIN_IRQ(7)	/* RTC Interrupt */

#define IRQ_EPPI0		BFIN_IRQ(8)	/* EPPI0 Interrupt (DMA12) */

#define IRQ_SPORT0_RX		BFIN_IRQ(9)	/* SPORT0 RX Interrupt (DMA0) */
@@ -89,15 +89,15 @@ Events (highest priority) EMU 0 
#define IRQ_MDMAS0		BFIN_IRQ(21)	/* MDMA Stream 0 Interrupt */

#define IRQ_MDMAS1		BFIN_IRQ(22)	/* MDMA Stream 1 Interrupt */

#define IRQ_WATCHDOG		BFIN_IRQ(23)	/* Watchdog Interrupt */

#define IRQ_DMAC1_ERR	BFIN_IRQ(24)	/* DMAC1 Status (Error) Interrupt */

#define IRQ_SPORT2_ERR	BFIN_IRQ(25)	/* SPORT2 Error Interrupt */

#define IRQ_SPORT3_ERR	BFIN_IRQ(26)	/* SPORT3 Error Interrupt */

#define IRQ_DMAC1_ERROR		BFIN_IRQ(24)	/* DMAC1 Status (Error) Interrupt */

#define IRQ_SPORT2_ERROR	BFIN_IRQ(25)	/* SPORT2 Error Interrupt */

#define IRQ_SPORT3_ERROR	BFIN_IRQ(26)	/* SPORT3 Error Interrupt */

#define IRQ_MXVR_DATA		BFIN_IRQ(27)	/* MXVR Data Interrupt */

#define IRQ_SPI1_ERR	BFIN_IRQ(28)	/* SPI1 Status (Error) Interrupt */

#define IRQ_SPI2_ERR	BFIN_IRQ(29)	/* SPI2 Status (Error) Interrupt */

#define IRQ_UART1_ERR	BFIN_IRQ(30)	/* UART1 Status (Error) Interrupt */

#define IRQ_UART2_ERR	BFIN_IRQ(31)	/* UART2 Status (Error) Interrupt */

#define IRQ_CAN0_ERR	BFIN_IRQ(32)	/* CAN0 Status (Error) Interrupt */

#define IRQ_SPI1_ERROR		BFIN_IRQ(28)	/* SPI1 Status (Error) Interrupt */

#define IRQ_SPI2_ERROR		BFIN_IRQ(29)	/* SPI2 Status (Error) Interrupt */

#define IRQ_UART1_ERROR		BFIN_IRQ(30)	/* UART1 Status (Error) Interrupt */

#define IRQ_UART2_ERROR		BFIN_IRQ(31)	/* UART2 Status (Error) Interrupt */

#define IRQ_CAN0_ERROR		BFIN_IRQ(32)	/* CAN0 Status (Error) Interrupt */

#define IRQ_SPORT2_RX		BFIN_IRQ(33)	/* SPORT2 RX (DMA18) Interrupt */

#define IRQ_SPORT2_TX		BFIN_IRQ(34)	/* SPORT2 TX (DMA19) Interrupt */

#define IRQ_SPORT3_RX		BFIN_IRQ(35)	/* SPORT3 RX (DMA20) Interrupt */
@@ -112,23 +112,22 @@ Events (highest priority) EMU 0 
#define IRQ_ATAPI_TX		BFIN_IRQ(44)	/* ATAPI TX (DMA11) Interrupt */

#define IRQ_TWI0		BFIN_IRQ(45)	/* TWI0 Interrupt */

#define IRQ_TWI1		BFIN_IRQ(46)	/* TWI1 Interrupt */

#define IRQ_TWI		IRQ_TWI0	/* TWI Interrupt */

#define IRQ_CAN0_RX		BFIN_IRQ(47)	/* CAN0 Receive Interrupt */

#define IRQ_CAN0_TX		BFIN_IRQ(48)	/* CAN0 Transmit Interrupt */

#define IRQ_MDMAS2		BFIN_IRQ(49)	/* MDMA Stream 2 Interrupt */

#define IRQ_MDMAS3		BFIN_IRQ(50)	/* MDMA Stream 3 Interrupt */

#define IRQ_MXVR_ERR	BFIN_IRQ(51)	/* MXVR Status (Error) Interrupt */

#define IRQ_MXVR_ERROR		BFIN_IRQ(51)	/* MXVR Status (Error) Interrupt */

#define IRQ_MXVR_MSG		BFIN_IRQ(52)	/* MXVR Message Interrupt */

#define IRQ_MXVR_PKT		BFIN_IRQ(53)	/* MXVR Packet Interrupt */

#define IRQ_EPP1_ERR	BFIN_IRQ(54)	/* EPPI1 Error Interrupt */

#define IRQ_EPP2_ERR	BFIN_IRQ(55)	/* EPPI2 Error Interrupt */

#define IRQ_UART3_ERR	BFIN_IRQ(56)	/* UART3 Status (Error) Interrupt */

#define IRQ_HOST_ERR	BFIN_IRQ(57)	/* HOST Status (Error) Interrupt */

#define IRQ_PIXC_ERR	BFIN_IRQ(59)	/* PIXC Status (Error) Interrupt */

#define IRQ_NFC_ERR	BFIN_IRQ(60)	/* NFC Error Interrupt */

#define IRQ_ATAPI_ERR	BFIN_IRQ(61)	/* ATAPI Error Interrupt */

#define IRQ_CAN1_ERR	BFIN_IRQ(62)	/* CAN1 Status (Error) Interrupt */

#define IRQ_HS_DMA_ERR	BFIN_IRQ(63)	/* Handshake DMA Status Interrupt */

#define IRQ_EPP1_ERROR		BFIN_IRQ(54)	/* EPPI1 Error Interrupt */

#define IRQ_EPP2_ERROR		BFIN_IRQ(55)	/* EPPI2 Error Interrupt */

#define IRQ_UART3_ERROR		BFIN_IRQ(56)	/* UART3 Status (Error) Interrupt */

#define IRQ_HOST_ERROR		BFIN_IRQ(57)	/* HOST Status (Error) Interrupt */

#define IRQ_PIXC_ERROR		BFIN_IRQ(59)	/* PIXC Status (Error) Interrupt */

#define IRQ_NFC_ERROR		BFIN_IRQ(60)	/* NFC Error Interrupt */

#define IRQ_ATAPI_ERROR		BFIN_IRQ(61)	/* ATAPI Error Interrupt */

#define IRQ_CAN1_ERROR		BFIN_IRQ(62)	/* CAN1 Status (Error) Interrupt */

#define IRQ_HS_DMA_ERROR	BFIN_IRQ(63)	/* Handshake DMA Status Interrupt */

#define IRQ_PIXC_IN0		BFIN_IRQ(64)	/* PIXC IN0 (DMA15) Interrupt */

#define IRQ_PIXC_IN1		BFIN_IRQ(65)	/* PIXC IN1 (DMA16) Interrupt */

#define IRQ_PIXC_OUT		BFIN_IRQ(66)	/* PIXC OUT (DMA17) Interrupt */
@@ -345,6 +344,34 @@ Events (highest priority) EMU 0 
#define NR_IRQS     (SYS_IRQS+1)

#endif



/* For compatibility reasons with existing code */



#define IRQ_DMAC0_ERR 		IRQ_DMAC0_ERROR

#define IRQ_EPPI0_ERR 		IRQ_EPPI0_ERROR

#define IRQ_SPORT0_ERR		IRQ_SPORT0_ERROR

#define IRQ_SPORT1_ERR		IRQ_SPORT1_ERROR

#define IRQ_SPI0_ERR  		IRQ_SPI0_ERROR

#define IRQ_UART0_ERR 		IRQ_UART0_ERROR

#define IRQ_DMAC1_ERR 		IRQ_DMAC1_ERROR

#define IRQ_SPORT2_ERR		IRQ_SPORT2_ERROR

#define IRQ_SPORT3_ERR		IRQ_SPORT3_ERROR

#define IRQ_SPI1_ERR  		IRQ_SPI1_ERROR

#define IRQ_SPI2_ERR  		IRQ_SPI2_ERROR

#define IRQ_UART1_ERR 		IRQ_UART1_ERROR

#define IRQ_UART2_ERR 		IRQ_UART2_ERROR

#define IRQ_CAN0_ERR  		IRQ_CAN0_ERROR

#define IRQ_MXVR_ERR  		IRQ_MXVR_ERROR

#define IRQ_EPP1_ERR  		IRQ_EPP1_ERROR

#define IRQ_EPP2_ERR  		IRQ_EPP2_ERROR

#define IRQ_UART3_ERR 		IRQ_UART3_ERROR

#define IRQ_HOST_ERR  		IRQ_HOST_ERROR

#define IRQ_PIXC_ERR  		IRQ_PIXC_ERROR

#define IRQ_NFC_ERR   		IRQ_NFC_ERROR

#define IRQ_ATAPI_ERR 		IRQ_ATAPI_ERROR

#define IRQ_CAN1_ERR  		IRQ_CAN1_ERROR

#define IRQ_HS_DMA_ERR		IRQ_HS_DMA_ERROR





#define IVG7            7

#define IVG8            8

#define IVG9            9