Merge branch 'fixes-dss' of... (55135dfb) · Commits · e / devices / android_kernel_teracube_2e

arch/arm/mach-omap2/Makefile

+1 −4

Original line number	Diff line number	Diff line
		@@ -4,7 +4,7 @@

		# Common support
		obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
		common.o gpio.o dma.o wd_timer.o
		common.o gpio.o dma.o wd_timer.o display.o

		omap-2-3-common = irq.o sdrc.o
		hwmod-common = omap_hwmod.o \
		@@ -264,7 +264,4 @@ smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
		obj-y += $(smsc911x-m) $(smsc911x-y)
		obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o

		disp-$(CONFIG_OMAP2_DSS) := display.o
		obj-y += $(disp-m) $(disp-y)

		obj-y += common-board-devices.o twl-common.o

arch/arm/mach-omap2/display.c

+159 −0

Original line number	Diff line number	Diff line
		@@ -27,8 +27,35 @@
		#include <plat/omap_hwmod.h>
		#include <plat/omap_device.h>
		#include <plat/omap-pm.h>
		#include <plat/common.h>

		#include "control.h"
		#include "display.h"

		#define DISPC_CONTROL 0x0040
		#define DISPC_CONTROL2 0x0238
		#define DISPC_IRQSTATUS 0x0018

		#define DSS_SYSCONFIG 0x10
		#define DSS_SYSSTATUS 0x14
		#define DSS_CONTROL 0x40
		#define DSS_SDI_CONTROL 0x44
		#define DSS_PLL_CONTROL 0x48

		#define LCD_EN_MASK (0x1 << 0)
		#define DIGIT_EN_MASK (0x1 << 1)

		#define FRAMEDONE_IRQ_SHIFT 0
		#define EVSYNC_EVEN_IRQ_SHIFT 2
		#define EVSYNC_ODD_IRQ_SHIFT 3
		#define FRAMEDONE2_IRQ_SHIFT 22
		#define FRAMEDONETV_IRQ_SHIFT 24

		/*
		* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
		* reset before deciding that something has gone wrong
		*/
		#define FRAMEDONE_IRQ_TIMEOUT 100

		static struct platform_device omap_display_device = {
		.name = "omapdss",
		@@ -172,3 +199,135 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)

		return r;
		}

		static void dispc_disable_outputs(void)
		{
		u32 v, irq_mask = 0;
		bool lcd_en, digit_en, lcd2_en = false;
		int i;
		struct omap_dss_dispc_dev_attr *da;
		struct omap_hwmod *oh;

		oh = omap_hwmod_lookup("dss_dispc");
		if (!oh) {
		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
		return;
		}

		if (!oh->dev_attr) {
		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
		return;
		}

		da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;

		/* store value of LCDENABLE and DIGITENABLE bits */
		v = omap_hwmod_read(oh, DISPC_CONTROL);
		lcd_en = v & LCD_EN_MASK;
		digit_en = v & DIGIT_EN_MASK;

		/* store value of LCDENABLE for LCD2 */
		if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		lcd2_en = v & LCD_EN_MASK;
		}

		if (!(lcd_en \| digit_en \| lcd2_en))
		return; /* no managers currently enabled */

		/*
		* If any manager was enabled, we need to disable it before
		* DSS clocks are disabled or DISPC module is reset
		*/
		if (lcd_en)
		irq_mask \|= 1 << FRAMEDONE_IRQ_SHIFT;

		if (digit_en) {
		if (da->has_framedonetv_irq) {
		irq_mask \|= 1 << FRAMEDONETV_IRQ_SHIFT;
		} else {
		irq_mask \|= 1 << EVSYNC_EVEN_IRQ_SHIFT \|
		1 << EVSYNC_ODD_IRQ_SHIFT;
		}
		}

		if (lcd2_en)
		irq_mask \|= 1 << FRAMEDONE2_IRQ_SHIFT;

		/*
		* clear any previous FRAMEDONE, FRAMEDONETV,
		* EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
		*/
		omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);

		/* disable LCD and TV managers */
		v = omap_hwmod_read(oh, DISPC_CONTROL);
		v &= ~(LCD_EN_MASK \| DIGIT_EN_MASK);
		omap_hwmod_write(v, oh, DISPC_CONTROL);

		/* disable LCD2 manager */
		if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL2);
		}

		i = 0;
		while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
		irq_mask) {
		i++;
		if (i > FRAMEDONE_IRQ_TIMEOUT) {
		pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
		break;
		}
		mdelay(1);
		}
		}

		#define MAX_MODULE_SOFTRESET_WAIT 10000
		int omap_dss_reset(struct omap_hwmod *oh)
		{
		struct omap_hwmod_opt_clk *oc;
		int c = 0;
		int i, r;

		if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
		pr_err("dss_core: hwmod data doesn't contain reset data\n");
		return -EINVAL;
		}

		for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
		clk_enable(oc->_clk);

		dispc_disable_outputs();

		/* clear SDI registers */
		if (cpu_is_omap3430()) {
		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
		}

		/*
		* clear DSS_CONTROL register to switch DSS clock sources to
		* PRCM clock, if any
		*/
		omap_hwmod_write(0x0, oh, DSS_CONTROL);

		omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
		& SYSS_RESETDONE_MASK),
		MAX_MODULE_SOFTRESET_WAIT, c);

		if (c == MAX_MODULE_SOFTRESET_WAIT)
		pr_warning("dss_core: waiting for reset to finish failed\n");
		else
		pr_debug("dss_core: softreset done\n");

		for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
		clk_disable(oc->_clk);

		r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;

		return r;
		}

arch/arm/mach-omap2/display.h

0 → 100644

+29 −0

Original line number	Diff line number	Diff line
		/*
		* display.h - OMAP2+ integration-specific DSS header
		*
		* Copyright (C) 2011 Texas Instruments, Inc.
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of the GNU General Public License version 2 as published by
		* the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful, but WITHOUT
		* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
		* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
		* more details.
		*
		* You should have received a copy of the GNU General Public License along with
		* this program. If not, see <http://www.gnu.org/licenses/>.
		*/

		#ifndef __ARCH_ARM_MACH_OMAP2_DISPLAY_H
		#define __ARCH_ARM_MACH_OMAP2_DISPLAY_H

		#include <linux/kernel.h>

		struct omap_dss_dispc_dev_attr {
		u8 manager_count;
		bool has_framedonetv_irq;
		};

		#endif

arch/arm/mach-omap2/omap_hwmod_2420_data.c

+14 −3

Original line number	Diff line number	Diff line
		@@ -875,6 +875,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
		};

		static struct omap_hwmod_opt_clk dss_opt_clks[] = {
		/*
		* The DSS HW needs all DSS clocks enabled during reset. The dss_core
		* driver does not use these clocks.
		*/
		{ .role = "tv_clk", .clk = "dss_54m_fck" },
		{ .role = "sys_clk", .clk = "dss2_fck" },
		};
		@@ -899,7 +903,7 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
		.slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
		.masters = omap2420_dss_masters,
		.masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
		.flags = HWMOD_NO_IDLEST,
		.flags = HWMOD_NO_IDLEST \| HWMOD_CONTROL_OPT_CLKS_IN_RESET,
		};

		/* l4_core -> dss_dispc */
		@@ -939,6 +943,7 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
		.slaves = omap2420_dss_dispc_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
		.flags = HWMOD_NO_IDLEST,
		.dev_attr = &omap2_3_dss_dispc_dev_attr
		};

		/* l4_core -> dss_rfbi */
		@@ -961,6 +966,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
		&omap2420_l4_core__dss_rfbi,
		};

		static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
		{ .role = "ick", .clk = "dss_ick" },
		};

		static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
		.name = "dss_rfbi",
		.class = &omap2_rfbi_hwmod_class,
		@@ -972,6 +981,8 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
		.module_offs = CORE_MOD,
		},
		},
		.opt_clks = dss_rfbi_opt_clks,
		.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
		.slaves = omap2420_dss_rfbi_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
		.flags = HWMOD_NO_IDLEST,
		@@ -981,7 +992,7 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
		static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
		.master = &omap2420_l4_core_hwmod,
		.slave = &omap2420_dss_venc_hwmod,
		.clk = "dss_54m_fck",
		.clk = "dss_ick",
		.addr = omap2_dss_venc_addrs,
		.fw = {
		.omap2 = {
		@@ -1001,7 +1012,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
		static struct omap_hwmod omap2420_dss_venc_hwmod = {
		.name = "dss_venc",
		.class = &omap2_venc_hwmod_class,
		.main_clk = "dss1_fck",
		.main_clk = "dss_54m_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,

arch/arm/mach-omap2/omap_hwmod_2430_data.c

+14 −3

Original line number	Diff line number	Diff line
		@@ -942,6 +942,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
		};

		static struct omap_hwmod_opt_clk dss_opt_clks[] = {
		/*
		* The DSS HW needs all DSS clocks enabled during reset. The dss_core
		* driver does not use these clocks.
		*/
		{ .role = "tv_clk", .clk = "dss_54m_fck" },
		{ .role = "sys_clk", .clk = "dss2_fck" },
		};
		@@ -966,7 +970,7 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
		.slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
		.masters = omap2430_dss_masters,
		.masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
		.flags = HWMOD_NO_IDLEST,
		.flags = HWMOD_NO_IDLEST \| HWMOD_CONTROL_OPT_CLKS_IN_RESET,
		};

		/* l4_core -> dss_dispc */
		@@ -1000,6 +1004,7 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
		.slaves = omap2430_dss_dispc_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
		.flags = HWMOD_NO_IDLEST,
		.dev_attr = &omap2_3_dss_dispc_dev_attr
		};

		/* l4_core -> dss_rfbi */
		@@ -1016,6 +1021,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
		&omap2430_l4_core__dss_rfbi,
		};

		static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
		{ .role = "ick", .clk = "dss_ick" },
		};

		static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
		.name = "dss_rfbi",
		.class = &omap2_rfbi_hwmod_class,
		@@ -1027,6 +1036,8 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
		.module_offs = CORE_MOD,
		},
		},
		.opt_clks = dss_rfbi_opt_clks,
		.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
		.slaves = omap2430_dss_rfbi_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
		.flags = HWMOD_NO_IDLEST,
		@@ -1036,7 +1047,7 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
		static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
		.master = &omap2430_l4_core_hwmod,
		.slave = &omap2430_dss_venc_hwmod,
		.clk = "dss_54m_fck",
		.clk = "dss_ick",
		.addr = omap2_dss_venc_addrs,
		.flags = OCPIF_SWSUP_IDLE,
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		@@ -1050,7 +1061,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
		static struct omap_hwmod omap2430_dss_venc_hwmod = {
		.name = "dss_venc",
		.class = &omap2_venc_hwmod_class,
		.main_clk = "dss1_fck",
		.main_clk = "dss_54m_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,