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Commit 54e30033 authored by Philippe Begnic's avatar Philippe Begnic Committed by Mike Turquette
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mfd: db8500: Update BML clock register for db8580



BML clock register address in DB8580 has changed.Defined a new address
under different name for DB8580.

Signed-off-by: default avatarPhilippe Begnic <philippe.begnic@st.com>
Acked-by: default avatarLee Jones <lee.jones@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 852bbba9
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+1 −0
Original line number Diff line number Diff line
@@ -480,6 +480,7 @@ struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
	CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
	CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
	CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
	CLK_MGT_ENTRY(BML8580CLK, PLL_DIV, true),
	CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
	CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
	CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@
#define PRCM_PER7CLK_MGT	(0x040)
#define PRCM_LCDCLK_MGT		(0x044)
#define PRCM_BMLCLK_MGT		(0x04C)
#define PRCM_BML8580CLK_MGT	(0x108)
#define PRCM_HSITXCLK_MGT	(0x050)
#define PRCM_HSIRXCLK_MGT	(0x054)
#define PRCM_HDMICLK_MGT	(0x058)
+1 −0
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@ enum prcmu_clock {
	PRCMU_G1CLK, /* Ux540 only */
	PRCMU_SDMMCHCLK,
	PRCMU_CAMCLK,
	PRCMU_BML8580CLK,
	PRCMU_NUM_REG_CLOCKS,
	PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
	PRCMU_CDCLK,