Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 531efffc authored by John W. Linville's avatar John W. Linville
Browse files

Merge branch 'for-john' of git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next

parents bbf71a8f b571a697

drivers/net/wireless/ath/ath5k/base.c

+5 −0
Original line number Diff line number Diff line
@@ -2369,6 +2369,9 @@ ath5k_tx_complete_poll_work(struct work_struct *work) 
	int i;

	bool needreset = false;



	if (!test_bit(ATH_STAT_STARTED, ah->status))

		return;



	mutex_lock(&ah->lock);



	for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
@@ -2676,6 +2679,7 @@ int ath5k_start(struct ieee80211_hw *hw) 
	mmiowb();

	mutex_unlock(&ah->lock);



	set_bit(ATH_STAT_STARTED, ah->status);

	ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,

			msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
@@ -2737,6 +2741,7 @@ void ath5k_stop(struct ieee80211_hw *hw) 


	ath5k_stop_tasklets(ah);



	clear_bit(ATH_STAT_STARTED, ah->status);

	cancel_delayed_work_sync(&ah->tx_complete_work);



	if (!ath5k_modparam_no_hw_rfkill_switch)

drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h

+70 −68
Original line number Diff line number Diff line
@@ -233,9 +233,9 @@ static const u32 ar9565_1p0_baseband_core[][2] = { 
	{0x00009d10, 0x01834061},

	{0x00009d14, 0x00c00400},

	{0x00009d18, 0x00000000},

	{0x00009e08, 0x0078230c},

	{0x00009e24, 0x990bb515},

	{0x00009e28, 0x126f0000},

	{0x00009e08, 0x0038230c},

	{0x00009e24, 0x9907b515},

	{0x00009e28, 0x126f0600},

	{0x00009e30, 0x06336f77},

	{0x00009e34, 0x6af6532f},

	{0x00009e38, 0x0cc80c00},
@@ -337,7 +337,7 @@ static const u32 ar9565_1p0_baseband_core[][2] = { 


static const u32 ar9565_1p0_baseband_postamble[][5] = {

	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */

	{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a800d},

	{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8009},

	{0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a01ae},

	{0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x63c640da},

	{0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x09143c81},
@@ -345,9 +345,9 @@ static const u32 ar9565_1p0_baseband_postamble[][5] = { 
	{0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},

	{0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},

	{0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0},

	{0x00009e04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},

	{0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000d8},

	{0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec86d2e},

	{0x00009e04, 0x00802020, 0x00802020, 0x00142020, 0x00142020},

	{0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},

	{0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},

	{0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3379605e, 0x33795d5e},

	{0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},

	{0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
@@ -450,6 +450,8 @@ static const u32 ar9565_1p0_soc_postamble[][5] = { 


static const u32 ar9565_1p0_Common_rx_gain_table[][2] = {

	/* Addr      allmodes  */

	{0x00004050, 0x00300300},

	{0x0000406c, 0x00100000},

	{0x0000a000, 0x00010000},

	{0x0000a004, 0x00030002},

	{0x0000a008, 0x00050004},
@@ -498,27 +500,27 @@ static const u32 ar9565_1p0_Common_rx_gain_table[][2] = { 
	{0x0000a0b4, 0x00000000},

	{0x0000a0b8, 0x00000000},

	{0x0000a0bc, 0x00000000},

	{0x0000a0c0, 0x001f0000},

	{0x0000a0c4, 0x01000101},

	{0x0000a0c8, 0x011e011f},

	{0x0000a0cc, 0x011c011d},

	{0x0000a0d0, 0x02030204},

	{0x0000a0d4, 0x02010202},

	{0x0000a0d8, 0x021f0200},

	{0x0000a0dc, 0x0302021e},

	{0x0000a0e0, 0x03000301},

	{0x0000a0e4, 0x031e031f},

	{0x0000a0e8, 0x0402031d},

	{0x0000a0ec, 0x04000401},

	{0x0000a0f0, 0x041e041f},

	{0x0000a0f4, 0x0502041d},

	{0x0000a0f8, 0x05000501},

	{0x0000a0fc, 0x051e051f},

	{0x0000a100, 0x06010602},

	{0x0000a104, 0x061f0600},

	{0x0000a108, 0x061d061e},

	{0x0000a10c, 0x07020703},

	{0x0000a110, 0x07000701},

	{0x0000a0c0, 0x00bf00a0},

	{0x0000a0c4, 0x11a011a1},

	{0x0000a0c8, 0x11be11bf},

	{0x0000a0cc, 0x11bc11bd},

	{0x0000a0d0, 0x22632264},

	{0x0000a0d4, 0x22612262},

	{0x0000a0d8, 0x227f2260},

	{0x0000a0dc, 0x4322227e},

	{0x0000a0e0, 0x43204321},

	{0x0000a0e4, 0x433e433f},

	{0x0000a0e8, 0x4462433d},

	{0x0000a0ec, 0x44604461},

	{0x0000a0f0, 0x447e447f},

	{0x0000a0f4, 0x5582447d},

	{0x0000a0f8, 0x55805581},

	{0x0000a0fc, 0x559e559f},

	{0x0000a100, 0x66816682},

	{0x0000a104, 0x669f6680},

	{0x0000a108, 0x669d669e},

	{0x0000a10c, 0x77627763},

	{0x0000a110, 0x77607761},

	{0x0000a114, 0x00000000},

	{0x0000a118, 0x00000000},

	{0x0000a11c, 0x00000000},
@@ -530,27 +532,27 @@ static const u32 ar9565_1p0_Common_rx_gain_table[][2] = { 
	{0x0000a134, 0x00000000},

	{0x0000a138, 0x00000000},

	{0x0000a13c, 0x00000000},

	{0x0000a140, 0x001f0000},

	{0x0000a144, 0x01000101},

	{0x0000a148, 0x011e011f},

	{0x0000a14c, 0x011c011d},

	{0x0000a150, 0x02030204},

	{0x0000a154, 0x02010202},

	{0x0000a158, 0x021f0200},

	{0x0000a15c, 0x0302021e},

	{0x0000a160, 0x03000301},

	{0x0000a164, 0x031e031f},

	{0x0000a168, 0x0402031d},

	{0x0000a16c, 0x04000401},

	{0x0000a170, 0x041e041f},

	{0x0000a174, 0x0502041d},

	{0x0000a178, 0x05000501},

	{0x0000a17c, 0x051e051f},

	{0x0000a180, 0x06010602},

	{0x0000a184, 0x061f0600},

	{0x0000a188, 0x061d061e},

	{0x0000a18c, 0x07020703},

	{0x0000a190, 0x07000701},

	{0x0000a140, 0x00bf00a0},

	{0x0000a144, 0x11a011a1},

	{0x0000a148, 0x11be11bf},

	{0x0000a14c, 0x11bc11bd},

	{0x0000a150, 0x22632264},

	{0x0000a154, 0x22612262},

	{0x0000a158, 0x227f2260},

	{0x0000a15c, 0x4322227e},

	{0x0000a160, 0x43204321},

	{0x0000a164, 0x433e433f},

	{0x0000a168, 0x4462433d},

	{0x0000a16c, 0x44604461},

	{0x0000a170, 0x447e447f},

	{0x0000a174, 0x5582447d},

	{0x0000a178, 0x55805581},

	{0x0000a17c, 0x559e559f},

	{0x0000a180, 0x66816682},

	{0x0000a184, 0x669f6680},

	{0x0000a188, 0x669d669e},

	{0x0000a18c, 0x77e677e7},

	{0x0000a190, 0x77e477e5},

	{0x0000a194, 0x00000000},

	{0x0000a198, 0x00000000},

	{0x0000a19c, 0x00000000},
@@ -770,7 +772,7 @@ static const u32 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table[][5] = { 


static const u32 ar9565_1p0_pciephy_clkreq_disable_L1[][2] = {

	/* Addr      allmodes  */

	{0x00018c00, 0x18213ede},

	{0x00018c00, 0x18212ede},

	{0x00018c04, 0x000801d8},

	{0x00018c08, 0x0003780c},

};
@@ -889,8 +891,8 @@ static const u32 ar9565_1p0_common_wo_xlna_rx_gain_table[][2] = { 
	{0x0000a180, 0x66816682},

	{0x0000a184, 0x669f6680},

	{0x0000a188, 0x669d669e},

	{0x0000a18c, 0x77627763},

	{0x0000a190, 0x77607761},

	{0x0000a18c, 0x77e677e7},

	{0x0000a190, 0x77e477e5},

	{0x0000a194, 0x00000000},

	{0x0000a198, 0x00000000},

	{0x0000a19c, 0x00000000},
@@ -1114,7 +1116,7 @@ static const u32 ar9565_1p0_modes_high_ob_db_tx_gain_table[][5] = { 
	{0x0000a2e0, 0xffecec00, 0xffecec00, 0xfd339c84, 0xfd339c84},

	{0x0000a2e4, 0xfc0f0000, 0xfc0f0000, 0xfec3e000, 0xfec3e000},

	{0x0000a2e8, 0xfc100000, 0xfc100000, 0xfffc0000, 0xfffc0000},

	{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},

	{0x0000a410, 0x000050d9, 0x000050d9, 0x000050df, 0x000050df},

	{0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},

	{0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},

	{0x0000a508, 0x0b022220, 0x0b022220, 0x08000004, 0x08000004},
@@ -1140,13 +1142,13 @@ static const u32 ar9565_1p0_modes_high_ob_db_tx_gain_table[][5] = { 
	{0x0000a558, 0x69027f56, 0x69027f56, 0x53001ce5, 0x53001ce5},

	{0x0000a55c, 0x6d029f56, 0x6d029f56, 0x57001ce9, 0x57001ce9},

	{0x0000a560, 0x73049f56, 0x73049f56, 0x5b001ceb, 0x5b001ceb},

	{0x0000a564, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},

	{0x0000a568, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},

	{0x0000a56c, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},

	{0x0000a570, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},

	{0x0000a574, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},

	{0x0000a578, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},

	{0x0000a57c, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},

	{0x0000a564, 0x7804ff56, 0x7804ff56, 0x60001cf0, 0x60001cf0},

	{0x0000a568, 0x7804ff56, 0x7804ff56, 0x61001cf1, 0x61001cf1},

	{0x0000a56c, 0x7804ff56, 0x7804ff56, 0x62001cf2, 0x62001cf2},

	{0x0000a570, 0x7804ff56, 0x7804ff56, 0x63001cf3, 0x63001cf3},

	{0x0000a574, 0x7804ff56, 0x7804ff56, 0x64001cf4, 0x64001cf4},

	{0x0000a578, 0x7804ff56, 0x7804ff56, 0x66001ff6, 0x66001ff6},

	{0x0000a57c, 0x7804ff56, 0x7804ff56, 0x66001ff6, 0x66001ff6},

	{0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},

	{0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},

	{0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -1174,7 +1176,7 @@ static const u32 ar9565_1p0_modes_high_power_tx_gain_table[][5] = { 
	{0x0000a2e0, 0xffecec00, 0xffecec00, 0xfd339c84, 0xfd339c84},

	{0x0000a2e4, 0xfc0f0000, 0xfc0f0000, 0xfec3e000, 0xfec3e000},

	{0x0000a2e8, 0xfc100000, 0xfc100000, 0xfffc0000, 0xfffc0000},

	{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},

	{0x0000a410, 0x000050d9, 0x000050d9, 0x000050df, 0x000050df},

	{0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},

	{0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},

	{0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
@@ -1200,13 +1202,13 @@ static const u32 ar9565_1p0_modes_high_power_tx_gain_table[][5] = { 
	{0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5},

	{0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9},

	{0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb},

	{0x0000a564, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},

	{0x0000a568, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},

	{0x0000a56c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},

	{0x0000a570, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},

	{0x0000a574, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},

	{0x0000a578, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},

	{0x0000a57c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},

	{0x0000a564, 0x7504ff56, 0x7504ff56, 0x59001cf0, 0x59001cf0},

	{0x0000a568, 0x7504ff56, 0x7504ff56, 0x5a001cf1, 0x5a001cf1},

	{0x0000a56c, 0x7504ff56, 0x7504ff56, 0x5b001cf2, 0x5b001cf2},

	{0x0000a570, 0x7504ff56, 0x7504ff56, 0x5c001cf3, 0x5c001cf3},

	{0x0000a574, 0x7504ff56, 0x7504ff56, 0x5d001cf4, 0x5d001cf4},

	{0x0000a578, 0x7504ff56, 0x7504ff56, 0x5f001ff6, 0x5f001ff6},

	{0x0000a57c, 0x7504ff56, 0x7504ff56, 0x5f001ff6, 0x5f001ff6},

	{0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},

	{0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},

	{0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},

drivers/net/wireless/ath/ath9k/main.c

+7 −3
Original line number Diff line number Diff line
@@ -226,13 +226,13 @@ static bool ath_complete_reset(struct ath_softc *sc, bool start) 
		if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))

			goto work;



		ath9k_set_beacon(sc);



		if (ah->opmode == NL80211_IFTYPE_STATION &&

		    test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {

			spin_lock_irqsave(&sc->sc_pm_lock, flags);

			sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;

			spin_unlock_irqrestore(&sc->sc_pm_lock, flags);

		} else {

			ath9k_set_beacon(sc);

		}

	work:

		ath_restart_work(sc);
@@ -1331,6 +1331,7 @@ static int ath9k_sta_add(struct ieee80211_hw *hw, 
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);

	struct ath_node *an = (struct ath_node *) sta->drv_priv;

	struct ieee80211_key_conf ps_key = { };

	int key;



	ath_node_attach(sc, sta, vif);
@@ -1338,7 +1339,9 @@ static int ath9k_sta_add(struct ieee80211_hw *hw, 
	    vif->type != NL80211_IFTYPE_AP_VLAN)

		return 0;



	an->ps_key = ath_key_config(common, vif, sta, &ps_key);

	key = ath_key_config(common, vif, sta, &ps_key);

	if (key > 0)

		an->ps_key = key;



	return 0;

}
@@ -1355,6 +1358,7 @@ static void ath9k_del_ps_key(struct ath_softc *sc, 
	    return;



	ath_key_delete(common, &ps_key);

	an->ps_key = 0;

}



static int ath9k_sta_remove(struct ieee80211_hw *hw,

drivers/net/wireless/b43/dma.c

+19 −0
Original line number Diff line number Diff line
@@ -1728,6 +1728,25 @@ static void dma_rx(struct b43_dmaring *ring, int *slot) 
	sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);

}



void b43_dma_handle_rx_overflow(struct b43_dmaring *ring)

{

	int current_slot, previous_slot;



	B43_WARN_ON(ring->tx);



	/* Device has filled all buffers, drop all packets and let TCP

	 * decrease speed.

	 * Decrement RX index by one will let the device to see all slots

	 * as free again

	 */

	/*

	*TODO: How to increase rx_drop in mac80211?

	*/

	current_slot = ring->ops->get_current_rxslot(ring);

	previous_slot = prev_slot(ring, current_slot);

	ring->ops->set_current_rxslot(ring, previous_slot);

}



void b43_dma_rx(struct b43_dmaring *ring)

{

	const struct b43_dma_ops *ops = ring->ops;

drivers/net/wireless/b43/dma.h

+3 −1
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ 
/* DMA-Interrupt reasons. */

#define B43_DMAIRQ_FATALMASK	((1 << 10) | (1 << 11) | (1 << 12) \

					 | (1 << 14) | (1 << 15))

#define B43_DMAIRQ_NONFATALMASK	(1 << 13)

#define B43_DMAIRQ_RDESC_UFLOW		(1 << 13)

#define B43_DMAIRQ_RX_DONE		(1 << 16)



/*** 32-bit DMA Engine. ***/
@@ -295,6 +295,8 @@ int b43_dma_tx(struct b43_wldev *dev, 
void b43_dma_handle_txstatus(struct b43_wldev *dev,

			     const struct b43_txstatus *status);



void b43_dma_handle_rx_overflow(struct b43_dmaring *ring);



void b43_dma_rx(struct b43_dmaring *ring);



void b43_dma_direct_fifo_rx(struct b43_wldev *dev,