[ARM] 4521/2: S3C: Reorganise VA mapping headers

#ifndef __ASM_ARCH_MAP_H

#define __ASM_ARCH_MAP_H

/* we have a bit of a tight squeeze to fit all our registers from

 * 0xF00000000 upwards, since we use all of the nGCS space in some

 * capacity, and also need to fit the S3C2410 registers in as well...

 *

 * we try to ensure stuff like the IRQ registers are available for

 * an single MOVS instruction (ie, only 8 bits of set data)

 *

 * Note, we are trying to remove some of these from the implementation

 * as they are only useful to certain drivers...

 */

#include <asm/plat-s3c/map.h>

#ifndef __ASSEMBLY__

#define S3C2410_ADDR(x)	  ((void __iomem __force *)0xF0000000 + (x))

#else

#define S3C2410_ADDR(x)	  (0xF0000000 + (x))

#endif

#define S3C2410_ADDR(x)		S3C_ADDR(x)

/* interrupt controller is the first thing we put in, to make

 * the assembly code for the irq detection easier

 */

#define S3C24XX_VA_IRQ	   S3C2410_ADDR(0x00000000)

#define S3C24XX_VA_IRQ	   S3C_VA_IRQ

#define S3C2410_PA_IRQ	   (0x4A000000)

#define S3C24XX_SZ_IRQ	   SZ_1M

/* memory controller registers */

#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)

#define S3C24XX_VA_MEMCTRL S3C_VA_MEM

#define S3C2410_PA_MEMCTRL (0x48000000)

#define S3C24XX_SZ_MEMCTRL SZ_1M

#define S3C24XX_SZ_DMA	   SZ_1M

/* Clock and Power management */

#define S3C24XX_VA_CLKPWR  S3C2410_ADDR(0x00200000)

#define S3C24XX_VA_CLKPWR  S3C_VA_SYS

#define S3C2410_PA_CLKPWR  (0x4C000000)

#define S3C24XX_SZ_CLKPWR  SZ_1M

#define S3C24XX_SZ_NAND	   SZ_1M

/* UARTs */

#define S3C24XX_VA_UART	   S3C2410_ADDR(0x00400000)

#define S3C24XX_VA_UART	   S3C_VA_UART

#define S3C2410_PA_UART	   (0x50000000)

#define S3C24XX_SZ_UART	   SZ_1M

/* Timers */

#define S3C24XX_VA_TIMER   S3C2410_ADDR(0x00500000)

#define S3C24XX_VA_TIMER   S3C_VA_TIMER

#define S3C2410_PA_TIMER   (0x51000000)

#define S3C24XX_SZ_TIMER   SZ_1M

#define S3C24XX_SZ_USBDEV  SZ_1M

/* Watchdog */

#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000)

#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG

#define S3C2410_PA_WATCHDOG (0x53000000)

#define S3C24XX_SZ_WATCHDOG SZ_1M

 * it is the same distance apart from the UART in the

 * phsyical address space, as the initial mapping for the IO

 * is done as a 1:1 maping. This puts it (currently) at

 * 0xF6800000, which is not in the way of any current mapping

 * 0xFA800000, which is not in the way of any current mapping

 * by the base system.

*/

#define S3C2410_SDRAM_PA    (S3C2410_CS6)

/* Use a single interface for common resources between S3C24XX cpus */

#define S3C24XX_PA_IRQ      S3C2410_PA_IRQ

/* linux/include/asm-arm/plat-s3c/map.h

 *

 * Copyright 2003, 2007 Simtec Electronics

 *	http://armlinux.simtec.co.uk/

 *	Ben Dooks <ben@simtec.co.uk>

 *

 * S3C - Memory map definitions (virtual addresses)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/

#ifndef __ASM_PLAT_MAP_H

#define __ASM_PLAT_MAP_H __FILE__

/* Fit all our registers in at 0xF4000000 upwards, trying to use as

 * little of the VA space as possible so vmalloc and friends have a

 * better chance of getting memory.

 *

 * we try to ensure stuff like the IRQ registers are available for

 * an single MOVS instruction (ie, only 8 bits of set data)

 */

#define S3C_ADDR_BASE	(0xF4000000)

#ifndef __ASSEMBLY__

#define S3C_ADDR(x)	((void __iomem __force *)S3C_ADDR_BASE + (x))

#else

#define S3C_ADDR(x)	(S3C_ADDR_BASE + (x))

#endif

#define S3C_VA_IRQ	S3C_ADDR(0x000000000)	/* irq controller(s) */

#define S3C_VA_SYS	S3C_ADDR(0x001000000)	/* system control */

#define S3C_VA_MEM	S3C_ADDR(0x002000000)	/* system control */

#define S3C_VA_TIMER	S3C_ADDR(0x003000000)	/* timer block */

#define S3C_VA_WATCHDOG	S3C_ADDR(0x004000000)	/* watchdog */

#define S3C_VA_UART	S3C_ADDR(0x010000000)	/* UART */

#endif /* __ASM_PLAT_MAP_H */

#ifndef __ASM_ARM_REGS_SERIAL_H

#define __ASM_ARM_REGS_SERIAL_H

#define S3C24XX_VA_UART0      (S3C24XX_VA_UART)

#define S3C24XX_VA_UART1      (S3C24XX_VA_UART + 0x4000 )

#define S3C24XX_VA_UART2      (S3C24XX_VA_UART + 0x8000 )

#define S3C24XX_VA_UART3      (S3C24XX_VA_UART + 0xC000 )

#define S3C24XX_VA_UART0      (S3C_VA_UART)

#define S3C24XX_VA_UART1      (S3C_VA_UART + 0x4000 )

#define S3C24XX_VA_UART2      (S3C_VA_UART + 0x8000 )

#define S3C24XX_VA_UART3      (S3C_VA_UART + 0xC000 )

#define S3C2410_PA_UART0      (S3C24XX_PA_UART)

#define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )

#ifndef __ASM_ARCH_REGS_TIMER_H

#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"

#define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x))

#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c))

#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))

#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))

#define S3C2410_TCFG0	      S3C2410_TIMERREG(0x00)

#define S3C2410_TCFG1	      S3C2410_TIMERREG(0x04)

#define S3C2410_TCON	      S3C2410_TIMERREG(0x08)

#define S3C2410_TCFG0	      S3C_TIMERREG(0x00)

#define S3C2410_TCFG1	      S3C_TIMERREG(0x04)

#define S3C2410_TCON	      S3C_TIMERREG(0x08)

#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)

#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)

/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */

#define S3C2410_TCNTB(tmr)    S3C2410_TIMERREG2(tmr, 0x00)

#define S3C2410_TCMPB(tmr)    S3C2410_TIMERREG2(tmr, 0x04)

#define S3C2410_TCNTO(tmr)    S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))

#define S3C2410_TCNTB(tmr)    S3C_TIMERREG2(tmr, 0x00)

#define S3C2410_TCMPB(tmr)    S3C_TIMERREG2(tmr, 0x04)

#define S3C2410_TCNTO(tmr)    S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))

#define S3C2410_TCON_T4RELOAD	  (1<<22)

#define S3C2410_TCON_T4MANUALUPD  (1<<21)

#ifndef __ASM_ARCH_REGS_WATCHDOG_H

#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"

#define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG)

#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)

#define S3C2410_WTCON	   S3C2410_WDOGREG(0x00)

#define S3C2410_WTDAT	   S3C2410_WDOGREG(0x04)

#define S3C2410_WTCNT	   S3C2410_WDOGREG(0x08)

#define S3C2410_WTCON	   S3C_WDOGREG(0x00)

#define S3C2410_WTDAT	   S3C_WDOGREG(0x04)

#define S3C2410_WTCNT	   S3C_WDOGREG(0x08)

/* the watchdog can either generate a reset pulse, or an

 * interrupt.