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Commit 529d235a authored by Michael Ellerman's avatar Michael Ellerman
Browse files

powerpc: Add a proper syscall for switching endianness



We currently have a "special" syscall for switching endianness. This is
syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall
exception entry.

That has a few problems, firstly the syscall number is outside of the
usual range, which confuses various tools. For example strace doesn't
recognise the syscall at all.

Secondly it's handled explicitly as a special case in the syscall
exception entry, which is complicated enough without it.

As a first step toward removing the special syscall, we need to add a
regular syscall that implements the same functionality.

The logic is simple, it simply toggles the MSR_LE bit in the userspace
MSR. This is the same as the special syscall, with the caveat that the
special syscall clobbers fewer registers.

This version clobbers r9-r12, XER, CTR, and CR0-1,5-7.

Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent c03e7374
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+1 −0
Original line number Diff line number Diff line
@@ -367,3 +367,4 @@ SYSCALL_SPU(getrandom)
SYSCALL_SPU(memfd_create)
SYSCALL_SPU(bpf)
COMPAT_SYS(execveat)
PPC64ONLY(switch_endian)
+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@
#include <uapi/asm/unistd.h>


#define __NR_syscalls		363
#define __NR_syscalls		364

#define __NR__exit __NR_exit
#define NR_syscalls	__NR_syscalls
+1 −0
Original line number Diff line number Diff line
@@ -385,5 +385,6 @@
#define __NR_memfd_create	360
#define __NR_bpf		361
#define __NR_execveat		362
#define __NR_switch_endian	363

#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */
+5 −0
Original line number Diff line number Diff line
@@ -356,6 +356,11 @@ _GLOBAL(ppc64_swapcontext)
	bl	sys_swapcontext
	b	.Lsyscall_exit

_GLOBAL(ppc_switch_endian)
	bl	save_nvgprs
	bl	sys_switch_endian
	b	.Lsyscall_exit

_GLOBAL(ret_from_fork)
	bl	schedule_tail
	REST_NVGPRS(r1)
+17 −0
Original line number Diff line number Diff line
@@ -121,3 +121,20 @@ long ppc_fadvise64_64(int fd, int advice, u32 offset_high, u32 offset_low,
	return sys_fadvise64(fd, (u64)offset_high << 32 | offset_low,
			     (u64)len_high << 32 | len_low, advice);
}

long sys_switch_endian(void)
{
	struct thread_info *ti;

	current->thread.regs->msr ^= MSR_LE;

	/*
	 * Set TIF_RESTOREALL so that r3 isn't clobbered on return to
	 * userspace. That also has the effect of restoring the non-volatile
	 * GPRs, so we saved them on the way in here.
	 */
	ti = current_thread_info();
	ti->flags |= _TIF_RESTOREALL;

	return 0;
}
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