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Commit 51f3547d authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: Allow SH-3 and SH-5 to use common headers. 



Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 93dc544c

arch/sh/include/cpu-sh3/cpu/addrspace.h

deleted100644 → 0
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/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 1999 by Kaz Kojima

 *

 * Defitions for the address spaces of the SH-3 CPUs.

 */

#ifndef __ASM_CPU_SH3_ADDRSPACE_H

#define __ASM_CPU_SH3_ADDRSPACE_H



#define P0SEG		0x00000000

#define P1SEG		0x80000000

#define P2SEG		0xa0000000

#define P3SEG		0xc0000000

#define P4SEG		0xe0000000



#endif /* __ASM_CPU_SH3_ADDRSPACE_H */

arch/sh/include/cpu-sh3/cpu/cacheflush.h

+1 −35
Original line number Original line Diff line number Diff line
@@ -10,25 +10,7 @@ 
#ifndef __ASM_CPU_SH3_CACHEFLUSH_H

#ifndef __ASM_CPU_SH3_CACHEFLUSH_H

#define __ASM_CPU_SH3_CACHEFLUSH_H

#define __ASM_CPU_SH3_CACHEFLUSH_H





/*

 * Cache flushing:

 *

 *  - flush_cache_all() flushes entire cache

 *  - flush_cache_mm(mm) flushes the specified mm context's cache lines

 *  - flush_cache_dup mm(mm) handles cache flushing when forking

 *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page

 *  - flush_cache_range(vma, start, end) flushes a range of pages

 *

 *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache

 *  - flush_icache_range(start, end) flushes(invalidates) a range for icache

 *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache

 *

 *  Caches are indexed (effectively) by physical address on SH-3, so

 *  we don't need them.

 */



#if defined(CONFIG_SH7705_CACHE_32KB)

#if defined(CONFIG_SH7705_CACHE_32KB)



/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the

/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the

 * SH4. Unlike the SH4 this is a unified cache so we need to do some work

 * SH4. Unlike the SH4 this is a unified cache so we need to do some work

 * in mmap when 'exec'ing a new binary

 * in mmap when 'exec'ing a new binary
@@ -48,23 +30,7 @@ void flush_dcache_page(struct page *pg); 
void flush_icache_range(unsigned long start, unsigned long end);

void flush_icache_range(unsigned long start, unsigned long end);

void flush_icache_page(struct vm_area_struct *vma, struct page *page);

void flush_icache_page(struct vm_area_struct *vma, struct page *page);

#else

#else

#define flush_cache_all()			do { } while (0)

#include <cpu-common/cpu/cacheflush.h>

#define flush_cache_mm(mm)			do { } while (0)

#define flush_cache_dup_mm(mm)			do { } while (0)

#define flush_cache_range(vma, start, end)	do { } while (0)

#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)

#define flush_dcache_page(page)			do { } while (0)

#define flush_icache_range(start, end)		do { } while (0)

#define flush_icache_page(vma,pg)		do { } while (0)

#endif

#endif





#define flush_dcache_mmap_lock(mapping)		do { } while (0)

#define flush_dcache_mmap_unlock(mapping)	do { } while (0)



/* SH3 has unified cache so no special action needed here */

#define flush_cache_sigtramp(vaddr)		do { } while (0)

#define flush_icache_user_range(vma,pg,adr,len)	do { } while (0)



#define p3_cache_init()				do { } while (0)



#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */
 
#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */

arch/sh/include/cpu-sh3/cpu/rtc.h

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#ifndef __ASM_SH_CPU_SH3_RTC_H

#define __ASM_SH_CPU_SH3_RTC_H



#define rtc_reg_size		sizeof(u16)

#define RTC_BIT_INVERTED	0	/* No bug on SH7708, SH7709A */

#define RTC_DEF_CAPABILITIES	0UL



#endif /* __ASM_SH_CPU_SH3_RTC_H */

arch/sh/include/cpu-sh3/cpu/sigcontext.h

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#ifndef __ASM_CPU_SH3_SIGCONTEXT_H

#define __ASM_CPU_SH3_SIGCONTEXT_H



struct sigcontext {

	unsigned long	oldmask;



	/* CPU registers */

	unsigned long sc_regs[16];

	unsigned long sc_pc;

	unsigned long sc_pr;

	unsigned long sc_sr;

	unsigned long sc_gbr;

	unsigned long sc_mach;

	unsigned long sc_macl;

};



#endif /* __ASM_CPU_SH3_SIGCONTEXT_H */