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Commit 513e7ecd authored by Helge Deller's avatar Helge Deller Committed by Kyle McMartin
Browse files

[PARISC] convert to use CONFIG_64BIT instead of __LP64__ 



Signed-off-by: default avatarHelge Deller <deller@gmx.de>
Signed-off-by: default avatarKyle McMartin <kyle@parisc-linux.org>
parent a8f44e38

include/asm-parisc/assembly.h

+6 −6
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ 


#ifdef __ASSEMBLY__



#ifdef __LP64__

#ifdef CONFIG_64BIT

/* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so

 * work around that for now... */

	.level 2.0w
@@ -164,7 +164,7 @@ 
	.endm



	.macro loadgp

#ifdef __LP64__

#ifdef CONFIG_64BIT

	ldil		L%__gp, %r27

	ldo		R%__gp(%r27), %r27

#else
@@ -342,7 +342,7 @@ 
	fldd,mb	-8(%r30),   %fr12

	.endm



#ifdef __LP64__

#ifdef CONFIG_64BIT

	.macro	callee_save

	std,ma	  %r3,	 CALLEE_REG_FRAME_SIZE(%r30)

	mfctl	  %cr27, %r3
@@ -385,7 +385,7 @@ 
	ldd,mb	-CALLEE_REG_FRAME_SIZE(%r30),    %r3

	.endm



#else /* ! __LP64__ */

#else /* ! CONFIG_64BIT */



	.macro	callee_save

	stw,ma	 %r3,	CALLEE_REG_FRAME_SIZE(%r30)
@@ -428,7 +428,7 @@ 
	mtctl	%r3, %cr27

	ldw,mb	-CALLEE_REG_FRAME_SIZE(%r30),   %r3

	.endm

#endif /* ! __LP64__ */

#endif /* ! CONFIG_64BIT */



	.macro	save_specials	regs
@@ -449,7 +449,7 @@ 
	mtctl	 %r0,	%cr18

	SAVE_CR  (%cr18, PT_IAOQ1(\regs))



#ifdef __LP64__

#ifdef CONFIG_64BIT

	/* cr11 (sar) is a funny one.  5 bits on PA1.1 and 6 bit on PA2.0

	 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only

	 * reads 5 bits.  Use mfctl,w to read all six bits.  Otherwise

include/asm-parisc/atomic.h

+6 −6
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ extern void __xchg_called_with_bad_pointer(void); 
/* __xchg32/64 defined in arch/parisc/lib/bitops.c */

extern unsigned long __xchg8(char, char *);

extern unsigned long __xchg32(int, int *);

#ifdef __LP64__

#ifdef CONFIG_64BIT

extern unsigned long __xchg64(unsigned long, unsigned long *);

#endif
@@ -67,7 +67,7 @@ static __inline__ unsigned long 
__xchg(unsigned long x, __volatile__ void * ptr, int size)

{

	switch(size) {

#ifdef __LP64__

#ifdef CONFIG_64BIT

	case 8: return __xchg64(x,(unsigned long *) ptr);

#endif

	case 4: return __xchg32((int) x, (int *) ptr);
@@ -81,7 +81,7 @@ __xchg(unsigned long x, __volatile__ void * ptr, int size) 
/*

** REVISIT - Abandoned use of LDCW in xchg() for now:

** o need to test sizeof(*ptr) to avoid clearing adjacent bytes

** o and while we are at it, could __LP64__ code use LDCD too?

** o and while we are at it, could CONFIG_64BIT code use LDCD too?

**

**	if (__builtin_constant_p(x) && (x == NULL))

**		if (((unsigned long)p & 0xf) == 0)
@@ -105,7 +105,7 @@ static __inline__ unsigned long 
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)

{

	switch(size) {

#ifdef __LP64__

#ifdef CONFIG_64BIT

	case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);

#endif

	case 4: return __cmpxchg_u32((unsigned int *)ptr, (unsigned int) old, (unsigned int) new_);
@@ -218,7 +218,7 @@ static __inline__ int atomic_read(const atomic_t *v) 
#define smp_mb__before_atomic_inc()	smp_mb()

#define smp_mb__after_atomic_inc()	smp_mb()



#ifdef __LP64__

#ifdef CONFIG_64BIT



typedef struct { volatile s64 counter; } atomic64_t;
@@ -270,7 +270,7 @@ atomic64_read(const atomic64_t *v) 
#define atomic64_dec_and_test(v)	(atomic64_dec_return(v) == 0)

#define atomic64_sub_and_test(i,v)	(atomic64_sub_return((i),(v)) == 0)



#endif /* __LP64__ */

#endif /* CONFIG_64BIT */



#include <asm-generic/atomic.h>

include/asm-parisc/bitops.h

+1 −1
Original line number Diff line number Diff line
@@ -136,7 +136,7 @@ static __inline__ unsigned long __ffs(unsigned long x) 
	unsigned long ret;



	__asm__(

#ifdef __LP64__

#ifdef CONFIG_64BIT

		" ldi       63,%1\n"

		" extrd,u,*<>  %0,63,32,%%r0\n"

		" extrd,u,*TR  %0,31,32,%0\n"	/* move top 32-bits down */

include/asm-parisc/elf.h

+1 −1
Original line number Diff line number Diff line
@@ -220,7 +220,7 @@ typedef struct elf64_fdesc { 
 * macros, and then it includes fs/binfmt_elf.c to provide an alternate

 * elf binary handler for 32 bit binaries (on the 64 bit kernel).

 */

#ifdef __LP64__

#ifdef CONFIG_64BIT

#define ELF_CLASS       ELFCLASS64

#else

#define ELF_CLASS	ELFCLASS32

include/asm-parisc/io.h

+2 −2
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ static inline unsigned long long gsc_readq(unsigned long addr) 
{

	unsigned long long ret;



#ifdef __LP64__

#ifdef CONFIG_64BIT

	__asm__ __volatile__(

	"	ldda	0(%1),%0\n"

	:  "=r" (ret) : "r" (addr) );
@@ -108,7 +108,7 @@ static inline void gsc_writel(unsigned int val, unsigned long addr) 


static inline void gsc_writeq(unsigned long long val, unsigned long addr)

{

#ifdef __LP64__

#ifdef CONFIG_64BIT

	__asm__ __volatile__(

	"	stda	%0,0(%1)\n"

	: :  "r" (val), "r" (addr) );