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Commit 50f4df4e authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
Browse files

Merge remote branch 'kumar/next' into merge

parents 12fcdba1 b49d81de
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+1 −1
Original line number Diff line number Diff line
@@ -109,7 +109,7 @@
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "fsl,mpc8315-immr", "simple-bus";
		compatible = "fsl,mpc8308-immr", "simple-bus";
		ranges = <0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <0>;
+2 −2
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@@ -291,13 +291,13 @@
			ranges = <0x0 0xc100 0x200>;
			cell-index = <1>;
			dma00: dma-channel@0 {
				compatible = "fsl,eloplus-dma-channel";
				compatible = "fsl,ssi-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupts = <76 2>;
			};
			dma01: dma-channel@80 {
				compatible = "fsl,eloplus-dma-channel";
				compatible = "fsl,ssi-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupts = <77 2>;
+15 −6
Original line number Diff line number Diff line
@@ -467,13 +467,22 @@ struct qe_immap {
extern struct qe_immap __iomem *qe_immr;
extern phys_addr_t get_qe_base(void);

static inline unsigned long immrbar_virt_to_phys(void *address)
/*
 * Returns the offset within the QE address space of the given pointer.
 *
 * Note that the QE does not support 36-bit physical addresses, so if
 * get_qe_base() returns a number above 4GB, the caller will probably fail.
 */
static inline phys_addr_t immrbar_virt_to_phys(void *address)
{
	if ( ((u32)address >= (u32)qe_immr) &&
			((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
		return (unsigned long)(address - (u32)qe_immr +
				(u32)get_qe_base());
	return (unsigned long)virt_to_phys(address);
	void *q = (void *)qe_immr;

	/* Is it a MURAM address? */
	if ((address >= q) && (address < (q + QE_IMMAP_SIZE)))
		return get_qe_base() + (address - q);

	/* It's an address returned by kmalloc */
	return virt_to_phys(address);
}

#endif /* __KERNEL__ */
+2 −0
Original line number Diff line number Diff line
@@ -283,6 +283,7 @@
#define HID0_NOPTI	(1<<0)		/* No-op dcbt and dcbst instr. */

#define SPRN_HID1	0x3F1		/* Hardware Implementation Register 1 */
#ifdef CONFIG_6xx
#define HID1_EMCP	(1<<31)		/* 7450 Machine Check Pin Enable */
#define HID1_DFS	(1<<22)		/* 7447A Dynamic Frequency Scaling */
#define HID1_PC0	(1<<16)		/* 7450 PLL_CFG[0] */
@@ -292,6 +293,7 @@
#define HID1_SYNCBE	(1<<11)		/* 7450 ABE for sync, eieio */
#define HID1_ABE	(1<<10)		/* 7450 Address Broadcast Enable */
#define HID1_PS		(1<<16)		/* 750FX PLL selection */
#endif
#define SPRN_HID2	0x3F8		/* Hardware Implementation Register 2 */
#define SPRN_HID2_GEKKO	0x398		/* Gekko HID2 Register */
#define SPRN_IABR	0x3F2	/* Instruction Address Breakpoint Register */
+14 −0
Original line number Diff line number Diff line
@@ -246,6 +246,20 @@
					store or cache line push */
#endif

/* Bit definitions for the HID1 */
#ifdef CONFIG_E500
/* e500v1/v2 */
#define HID1_PLL_CFG_MASK 0xfc000000	/* PLL_CFG input pins */
#define HID1_RFXE	0x00020000	/* Read fault exception enable */
#define HID1_R1DPE	0x00008000	/* R1 data bus parity enable */
#define HID1_R2DPE	0x00004000	/* R2 data bus parity enable */
#define HID1_ASTME	0x00002000	/* Address bus streaming mode enable */
#define HID1_ABE	0x00001000	/* Address broadcast enable */
#define HID1_MPXTT	0x00000400	/* MPX re-map transfer type */
#define HID1_ATS	0x00000080	/* Atomic status */
#define HID1_MID_MASK	0x0000000f	/* MID input pins */
#endif

/* Bit definitions for the DBSR. */
/*
 * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
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