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Commit 5011a7e8 authored by Alban Bedel's avatar Alban Bedel Committed by Ralf Baechle
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MIPS: ath79: Fix the DDR control initialization on ar71xx and ar934x 



The DDR control initialization needs to know the SoC type, however
ath79_detect_sys_type() was called after ath79_ddr_ctrl_init().
Reverse the order to fix the DDR control initialization on ar71xx and
ar934x.

Signed-off-by: default avatarAlban Bedel <albeu@free.fr>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
CC: stable@vger.kernel.org # v4.2+
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11500/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 95486e49

arch/mips/ath79/setup.c

+1 −1
Original line number Diff line number Diff line
@@ -216,9 +216,9 @@ void __init plat_mem_setup(void) 
					   AR71XX_RESET_SIZE);

	ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,

					 AR71XX_PLL_SIZE);

	ath79_detect_sys_type();

	ath79_ddr_ctrl_init();



	ath79_detect_sys_type();

	if (mips_machtype != ATH79_MACH_GENERIC_OF)

		detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);