Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4f985b4c authored by Maxime Ripard's avatar Maxime Ripard Committed by Mike Turquette
Browse files

clk: sun5i: Add compatibles for Allwinner A13 



The A13 has a lot less clocks than the one found in the Allwinner A10.
Add these stripped down clocks to the clock driver and in the
documentation.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: default avatarEmilio López <emilio@elopez.com.ar>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 20faa59e

Documentation/devicetree/bindings/clock/sunxi.txt

+13 −104
Original line number Diff line number Diff line
@@ -12,22 +12,30 @@ Required properties: 
	"allwinner,sun4i-axi-clk" - for the AXI clock

	"allwinner,sun4i-axi-gates-clk" - for the AXI gates

	"allwinner,sun4i-ahb-clk" - for the AHB clock

	"allwinner,sun4i-ahb-gates-clk" - for the AHB gates

	"allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10

	"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13

	"allwinner,sun4i-apb0-clk" - for the APB0 clock

	"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates

	"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10

	"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13

	"allwinner,sun4i-apb1-clk" - for the APB1 clock

	"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing

	"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates

	"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10

	"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13



Required properties for all clocks:

- reg : shall be the control register address for the clock.

- clocks : shall be the input parent clock(s) phandle for the clock

- #clock-cells : from common clock binding; shall be set to 0 except for

	"allwinner,sun4i-*-gates-clk" where it shall be set to 1

	"allwinner,*-gates-clk" where it shall be set to 1



Additionally, "allwinner,sun4i-*-gates-clk" clocks require:

Additionally, "allwinner,*-gates-clk" clocks require:

- clock-output-names : the corresponding gate names that the clock controls



Clock consumers should specify the desired clocks they use with a

"clocks" phandle cell. Consumers that are using a gated clock should

provide an additional ID in their clock property. The values of this

ID are documented in sunxi/<soc>-gates.txt.



For example:



osc24M: osc24M@01c20050 {
@@ -50,102 +58,3 @@ cpu: cpu@01c20054 { 
	reg = <0x01c20054 0x4>;

	clocks = <&osc32k>, <&osc24M>, <&pll1>;

};
 






Gate clock outputs



The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;

their corresponding offsets as present on sun4i are listed below. Note that

some of these gates are not present on sun5i.



  * AXI gates ("allwinner,sun4i-axi-gates-clk")



    DRAM                                                                0



  * AHB gates ("allwinner,sun4i-ahb-gates-clk")



    USB0                                                                0

    EHCI0                                                               1

    OHCI0                                                               2*

    EHCI1                                                               3

    OHCI1                                                               4*

    SS                                                                  5

    DMA                                                                 6

    BIST                                                                7

    MMC0                                                                8

    MMC1                                                                9

    MMC2                                                                10

    MMC3                                                                11

    MS                                                                  12**

    NAND                                                                13

    SDRAM                                                               14



    ACE                                                                 16

    EMAC                                                                17

    TS                                                                  18



    SPI0                                                                20

    SPI1                                                                21

    SPI2                                                                22

    SPI3                                                                23

    PATA                                                                24

    SATA                                                                25**

    GPS                                                                 26*



    VE                                                                  32

    TVD                                                                 33

    TVE0                                                                34

    TVE1                                                                35

    LCD0                                                                36

    LCD1                                                                37



    CSI0                                                                40

    CSI1                                                                41



    HDMI                                                                43

    DE_BE0                                                              44

    DE_BE1                                                              45

    DE_FE0                                                              46

    DE_FE1                                                              47



    MP                                                                  50



    MALI400                                                             52



  * APB0 gates ("allwinner,sun4i-apb0-gates-clk")



    CODEC                                                               0

    SPDIF                                                               1*

    AC97                                                                2

    IIS                                                                 3



    PIO                                                                 5

    IR0                                                                 6

    IR1                                                                 7



    KEYPAD                                                              10



  * APB1 gates ("allwinner,sun4i-apb1-gates-clk")



    I2C0                                                                0

    I2C1                                                                1

    I2C2                                                                2



    CAN                                                                 4

    SCR                                                                 5

    PS20                                                                6

    PS21                                                                7



    UART0                                                               16

    UART1                                                               17

    UART2                                                               18

    UART3                                                               19

    UART4                                                               20

    UART5                                                               21

    UART6                                                               22

    UART7                                                               23



Notation:

 [*]:  The datasheet didn't mention these, but they are present on AW code

 [**]: The datasheet had this marked as "NC" but they are used on AW code

Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt

0 → 100644
+93 −0
Original line number Diff line number Diff line 
Gate clock outputs

------------------



  * AXI gates ("allwinner,sun4i-axi-gates-clk")



    DRAM					0



  * AHB gates ("allwinner,sun4i-ahb-gates-clk")



    USB0					0

    EHCI0					1

    OHCI0					2*

    EHCI1					3

    OHCI1					4*

    SS						5

    DMA						6

    BIST					7

    MMC0					8

    MMC1					9

    MMC2					10

    MMC3					11

    MS						12**

    NAND					13

    SDRAM					14



    ACE						16

    EMAC					17

    TS						18



    SPI0					20

    SPI1					21

    SPI2					22

    SPI3					23

    PATA					24

    SATA					25**

    GPS						26*



    VE						32

    TVD						33

    TVE0					34

    TVE1					35

    LCD0					36

    LCD1					37



    CSI0					40

    CSI1					41



    HDMI					43

    DE_BE0					44

    DE_BE1					45

    DE_FE1					46

    DE_FE1					47



    MP						50



    MALI400					52



  * APB0 gates ("allwinner,sun4i-apb0-gates-clk")



    CODEC					0

    SPDIF					1*

    AC97					2

    IIS						3



    PIO						5

    IR0						6

    IR1						7



    KEYPAD					10



  * APB1 gates ("allwinner,sun4i-apb1-gates-clk")



    I2C0					0

    I2C1					1

    I2C2					2



    CAN						4

    SCR						5

    PS20					6

    PS21					7



    UART0					16

    UART1					17

    UART2					18

    UART3					19

    UART4					20

    UART5					21

    UART6					22

    UART7					23



Notation:

 [*]:  The datasheet didn't mention these, but they are present on AW code

 [**]: The datasheet had this marked as "NC" but they are used on AW code

Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt

0 → 100644
+58 −0
Original line number Diff line number Diff line 
Gate clock outputs

------------------



  * AXI gates ("allwinner,sun4i-axi-gates-clk")



    DRAM					0



  * AHB gates ("allwinner,sun5i-a13-ahb-gates-clk")



    USBOTG					0

    EHCI					1

    OHCI					2



    SS						5

    DMA						6

    BIST					7

    MMC0					8

    MMC1					9

    MMC2					10



    NAND					13

    SDRAM					14



    SPI0					20

    SPI1					21

    SPI2					22



    STIMER					28



    VE						32



    LCD						36



    CSI						40



    DE_BE					44



    DE_FE					46



    IEP						51

    MALI400					52



  * APB0 gates ("allwinner,sun5i-a13-apb0-gates-clk")



    CODEC					0



    PIO						5

    IR						6



  * APB1 gates ("allwinner,sun5i-a13-apb1-gates-clk")



    I2C0					0

    I2C1					1

    I2C2					2



    UART1					17



    UART3					19

drivers/clk/sunxi/clk-sunxi.c

+23 −8
Original line number Diff line number Diff line
@@ -333,22 +333,34 @@ struct gates_data { 
	DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);

};



static const __initconst struct gates_data axi_gates_data = {

static const __initconst struct gates_data sun4i_axi_gates_data = {

	.mask = {1},

};



static const __initconst struct gates_data ahb_gates_data = {

static const __initconst struct gates_data sun4i_ahb_gates_data = {

	.mask = {0x7F77FFF, 0x14FB3F},

};



static const __initconst struct gates_data apb0_gates_data = {

static const __initconst struct gates_data sun5i_a13_ahb_gates_data = {

	.mask = {0x107067e7, 0x185111},

};



static const __initconst struct gates_data sun4i_apb0_gates_data = {

	.mask = {0x4EF},

};



static const __initconst struct gates_data apb1_gates_data = {

static const __initconst struct gates_data sun5i_a13_apb0_gates_data = {

	.mask = {0x61},

};



static const __initconst struct gates_data sun4i_apb1_gates_data = {

	.mask = {0xFF00F7},

};



static const __initconst struct gates_data sun5i_a13_apb1_gates_data = {

	.mask = {0xa0007},

};



static void __init sunxi_gates_clk_setup(struct device_node *node,

					 struct gates_data *data)

{
@@ -428,10 +440,13 @@ static const __initconst struct of_device_id clk_mux_match[] = { 


/* Matches for gate clocks */

static const __initconst struct of_device_id clk_gates_match[] = {

	{.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},

	{.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},

	{.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},

	{.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},

	{.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},

	{.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},

	{.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},

	{.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},

	{.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},

	{.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},

	{.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},

	{}

};