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Commit 4e68f5a7 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Paul Walmsley
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ARM: OMAP3: Fix CM register bit masks 



The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL
register are 3 bits wide.  Fix the MASK definition accordingly.

Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 96566043

arch/arm/mach-omap2/cm-regbits-34xx.h

+2 −2
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ 


/* CM_CLKSEL1_PLL_IVA2 */

#define OMAP3430_IVA2_CLK_SRC_SHIFT			19

#define OMAP3430_IVA2_CLK_SRC_MASK			(0x3 << 19)

#define OMAP3430_IVA2_CLK_SRC_MASK			(0x7 << 19)

#define OMAP3430_IVA2_DPLL_MULT_SHIFT			8

#define OMAP3430_IVA2_DPLL_MULT_MASK			(0x7ff << 8)

#define OMAP3430_IVA2_DPLL_DIV_SHIFT			0
@@ -124,7 +124,7 @@ 


/* CM_CLKSEL1_PLL_MPU */

#define OMAP3430_MPU_CLK_SRC_SHIFT			19

#define OMAP3430_MPU_CLK_SRC_MASK			(0x3 << 19)

#define OMAP3430_MPU_CLK_SRC_MASK			(0x7 << 19)

#define OMAP3430_MPU_DPLL_MULT_SHIFT			8

#define OMAP3430_MPU_DPLL_MULT_MASK			(0x7ff << 8)

#define OMAP3430_MPU_DPLL_DIV_SHIFT			0