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Commit 4e289a7d authored by Ludovic Desroches's avatar Ludovic Desroches Committed by Ulf Hansson
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mmc: sdhci-of-at91: Implement specific ->set_clock() function 



Disabling the internal clock while configuring the SD card clock can
lead to internal clock stabilization issue and/or unexpected switch to
the base clock when using presets.
A quirk SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST was introduced to fix
these bugs. The cause was assumed to be a too long internal
re-synchronisation but it seems in some cases the delay (even if longer)
doesn't fix this bug. The safest workaround is to not disable/enable the
internal clock during the SD card clock configuration.

Signed-off-by: default avatarLudovic Desroches <ludovic.desroches@atmel.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent fb9ee047

drivers/mmc/host/sdhci-of-at91.c

+46 −2
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
 */



#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/mmc/host.h>
@@ -37,8 +38,52 @@ struct sdhci_at91_priv { 
	struct clk *mainck;

};



static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)

{

	u16 clk;

	unsigned long timeout;



	host->mmc->actual_clock = 0;



	/*

	 * There is no requirement to disable the internal clock before

	 * changing the SD clock configuration. Moreover, disabling the

	 * internal clock, changing the configuration and re-enabling the

	 * internal clock causes some bugs. It can prevent to get the internal

	 * clock stable flag ready and an unexpected switch to the base clock

	 * when using presets.

	 */

	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);

	clk &= SDHCI_CLOCK_INT_EN;

	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);



	if (clock == 0)

		return;



	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);



	clk |= SDHCI_CLOCK_INT_EN;

	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);



	/* Wait max 20 ms */

	timeout = 20;

	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))

		& SDHCI_CLOCK_INT_STABLE)) {

		if (timeout == 0) {

			pr_err("%s: Internal clock never stabilised.\n",

			       mmc_hostname(host->mmc));

			return;

		}

		timeout--;

		mdelay(1);

	}



	clk |= SDHCI_CLOCK_CARD_EN;

	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

}



static const struct sdhci_ops sdhci_at91_sama5d2_ops = {

	.set_clock		= sdhci_set_clock,

	.set_clock		= sdhci_at91_set_clock,

	.set_bus_width		= sdhci_set_bus_width,

	.reset			= sdhci_reset,

	.set_uhs_signaling	= sdhci_set_uhs_signaling,
@@ -46,7 +91,6 @@ static const struct sdhci_ops sdhci_at91_sama5d2_ops = { 


static const struct sdhci_pltfm_data soc_data_sama5d2 = {

	.ops = &sdhci_at91_sama5d2_ops,

	.quirks2 = SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST,

};



static const struct of_device_id sdhci_at91_dt_match[] = {