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Commit 4e04632e authored by Akash Goel's avatar Akash Goel Committed by Daniel Vetter
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drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush' 



On Gen4+ platforms (except BDW), Render Cache Operational flush
cannot be enabled.
This WA is apparently required for all Gen4+ platforms,except BDW.
In BDW, the bit has been repurposed otherwise.
This has been tested only on vlv.

v2: Corrected the code regarding the wrong usage of
MASKED_BIT_DISABLE (Chris)

v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville)

v4: Adding WA for g4x, crestline, broadwater (Ville)

Signed-off-by: default avatarAkash Goel <akash.goel@intel.com>
Signed-off-by: default avatarSourab Gupta <sourab.gupta@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 8cbf3202

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -1061,6 +1061,7 @@ enum punit_power_well { 
#define   ECO_FLIP_DONE		(1<<0)



#define CACHE_MODE_0_GEN7	0x7000 /* IVB+ */

#define RC_OP_FLUSH_ENABLE (1<<0)

#define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)

#define CACHE_MODE_1		0x7004 /* IVB+ */

#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1<<6)

drivers/gpu/drm/i915/intel_pm.c

+24 −0
Original line number Diff line number Diff line
@@ -4625,6 +4625,9 @@ static void ironlake_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(CACHE_MODE_0,

		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));



	/* WaDisable_RenderCache_OperationalFlush:ilk */

	I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));



	g4x_disable_trickle_feed(dev);



	ibx_init_clock_gating(dev);
@@ -4700,6 +4703,9 @@ static void gen6_init_clock_gating(struct drm_device *dev) 
		I915_WRITE(GEN6_GT_MODE,

			   _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));



	/* WaDisable_RenderCache_OperationalFlush:snb */

	I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));



	/*

	 * BSpec recoomends 8x4 when MSAA is used,

	 * however in practice 16x4 seems fastest.
@@ -4939,6 +4945,9 @@ static void haswell_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN7_FF_THREAD_MODE,

		   I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);



	/* WaDisable_RenderCache_OperationalFlush:hsw */

	I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));



	/* enable HiZ Raw Stall Optimization */

	I915_WRITE(CACHE_MODE_0_GEN7,

		   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
@@ -4991,6 +5000,9 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,

			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));



	/* WaDisable_RenderCache_OperationalFlush:ivb */

	I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));



	/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */

	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,

		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
@@ -5106,6 +5118,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
		   _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |

				      GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));



	/* WaDisable_RenderCache_OperationalFlush:vlv */

	I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));



	/* WaForceL3Serialization:vlv */

	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &

		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
@@ -5175,6 +5190,9 @@ static void g4x_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(CACHE_MODE_0,

		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));



	/* WaDisable_RenderCache_OperationalFlush:g4x */

	I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));



	g4x_disable_trickle_feed(dev);

}
@@ -5189,6 +5207,9 @@ static void crestline_init_clock_gating(struct drm_device *dev) 
	I915_WRITE16(DEUC, 0);

	I915_WRITE(MI_ARB_STATE,

		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));



	/* WaDisable_RenderCache_OperationalFlush:gen4 */

	I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));

}



static void broadwater_init_clock_gating(struct drm_device *dev)
@@ -5203,6 +5224,9 @@ static void broadwater_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(RENCLK_GATE_D2, 0);

	I915_WRITE(MI_ARB_STATE,

		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));



	/* WaDisable_RenderCache_OperationalFlush:gen4 */

	I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));

}



static void gen3_init_clock_gating(struct drm_device *dev)