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Commit 4df49d9e authored by Simon Horman's avatar Simon Horman
Browse files

Merge tag 'renesas-r8a73a4-dt-timers-for-v3.19' into dt-for-v3.19.base 

Renesas ARM Based SoC r8a73a4 DT Timers Updates for v3.19

* Initialise CMT1 timer using DT
parents 0ee56d40 fd3edcbe

arch/arm/boot/dts/Makefile

+8 −8
Original line number Diff line number Diff line
@@ -376,25 +376,25 @@ dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \ 
	s5pv210-smdkc110.dtb \

	s5pv210-smdkv210.dtb \

	s5pv210-torbreck.dtb

dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \

dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \

	r8a73a4-ape6evm.dtb \

	r8a73a4-ape6evm-reference.dtb \

	r8a7740-armadillo800eva.dtb \

	r8a7778-bockw.dtb \

	r8a7778-bockw-reference.dtb \

	r8a7779-marzen.dtb \

	r8a7791-koelsch.dtb \

	r8a7790-lager.dtb \

	r8a7791-koelsch.dtb \

	sh7372-mackerel.dtb \

	sh73a0-kzm9g.dtb \

	sh73a0-kzm9g-reference.dtb \

	r8a73a4-ape6evm.dtb \

	r8a73a4-ape6evm-reference.dtb \

	sh7372-mackerel.dtb

	sh73a0-kzm9g-reference.dtb

dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \

	r7s72100-genmai.dtb \

	r8a7740-armadillo800eva.dtb \

	r8a7779-marzen.dtb \

	r8a7790-lager.dtb \

	r8a7791-henninger.dtb \

	r8a7791-koelsch.dtb \

	r8a7790-lager.dtb \

	r8a7779-marzen.dtb \

	r8a7794-alt.dtb

dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \

	socfpga_cyclone5_socdk.dtb \

arch/arm/boot/dts/emev2-kzm9d.dts

+32 −31
Original line number Diff line number Diff line
@@ -25,37 +25,7 @@ 


	chosen {

		bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp";

	};



	reg_1p8v: regulator@0 {

		compatible = "regulator-fixed";

		regulator-name = "fixed-1.8V";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;

		regulator-always-on;

		regulator-boot-on;

	};



	reg_3p3v: regulator@1 {

		compatible = "regulator-fixed";

		regulator-name = "fixed-3.3V";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		regulator-always-on;

		regulator-boot-on;

	};



	lan9220@20000000 {

		compatible = "smsc,lan9220", "smsc,lan9115";

		reg = <0x20000000 0x10000>;

		phy-mode = "mii";

		interrupt-parent = <&gpio0>;

		interrupts = <1 IRQ_TYPE_EDGE_RISING>;

		reg-io-width = <4>;

		smsc,irq-active-high;

		smsc,irq-push-pull;

		vddvario-supply = <&reg_1p8v>;

		vdd33a-supply = <&reg_3p3v>;

		stdout-path = &uart1;

	};



	gpio_keys {
@@ -92,4 +62,35 @@ 
			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;

		};

	};



	reg_1p8v: regulator@0 {

		compatible = "regulator-fixed";

		regulator-name = "fixed-1.8V";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;

		regulator-always-on;

		regulator-boot-on;

	};



	reg_3p3v: regulator@1 {

		compatible = "regulator-fixed";

		regulator-name = "fixed-3.3V";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		regulator-always-on;

		regulator-boot-on;

	};



	lan9220@20000000 {

		compatible = "smsc,lan9220", "smsc,lan9115";

		reg = <0x20000000 0x10000>;

		phy-mode = "mii";

		interrupt-parent = <&gpio0>;

		interrupts = <1 IRQ_TYPE_EDGE_RISING>;

		reg-io-width = <4>;

		smsc,irq-active-high;

		smsc,irq-push-pull;

		vddvario-supply = <&reg_1p8v>;

		vdd33a-supply = <&reg_3p3v>;

	};

};

arch/arm/boot/dts/emev2.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ 
			     <0 121 IRQ_TYPE_LEVEL_HIGH>;

	};



	smu@e0110000 {

	clocks@e0110000 {

		compatible = "renesas,emev2-smu";

		reg = <0xe0110000 0x10000>;

		#address-cells = <2>;
@@ -129,7 +129,7 @@ 
		};

	};



	sti@e0180000 {

	timer@e0180000 {

		compatible = "renesas,em-sti";

		reg = <0xe0180000 0x54>;

		interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
@@ -137,7 +137,7 @@ 
		clock-names = "sclk";

	};



	uart@e1020000 {

	uart0: serial@e1020000 {

		compatible = "renesas,em-uart";

		reg = <0xe1020000 0x38>;

		interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -145,7 +145,7 @@ 
		clock-names = "sclk";

	};



	uart@e1030000 {

	uart1: serial@e1030000 {

		compatible = "renesas,em-uart";

		reg = <0xe1030000 0x38>;

		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
@@ -153,7 +153,7 @@ 
		clock-names = "sclk";

	};



	uart@e1040000 {

	uart2: serial@e1040000 {

		compatible = "renesas,em-uart";

		reg = <0xe1040000 0x38>;

		interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
@@ -161,7 +161,7 @@ 
		clock-names = "sclk";

	};



	uart@e1050000 {

	uart3: serial@e1050000 {

		compatible = "renesas,em-uart";

		reg = <0xe1050000 0x38>;

		interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/r7s72100-genmai.dts

+2 −1
Original line number Diff line number Diff line
@@ -21,7 +21,8 @@ 
	};



	chosen {

		bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";

		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";

		stdout-path = &scif2;

	};



	memory {

arch/arm/boot/dts/r7s72100.dtsi

+101 −101
Original line number Diff line number Diff line
@@ -52,16 +52,6 @@ 
			clock-output-names = "usb_x1";

		};



		/* Special CPG clocks */

		cpg_clocks: cpg_clocks@fcfe0000 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-cpg-clocks",

				     "renesas,rz-cpg-clocks";

			reg = <0xfcfe0000 0x18>;

			clocks = <&extal_clk>, <&usb_x1_clk>;

			clock-output-names = "pll", "i", "g";

		};



		/* Fixed factor clocks */

		b_clk: b_clk {

			#clock-cells = <0>;
@@ -88,6 +78,16 @@ 
			clock-output-names = "p0";

		};



		/* Special CPG clocks */

		cpg_clocks: cpg_clocks@fcfe0000 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-cpg-clocks",

				     "renesas,rz-cpg-clocks";

			reg = <0xfcfe0000 0x18>;

			clocks = <&extal_clk>, <&usb_x1_clk>;

			clock-output-names = "pll", "i", "g";

		};



		/* MSTP clocks */

		mstp3_clks: mstp3_clks@fcfe0420 {

			#clock-cells = <1>;
@@ -148,97 +148,6 @@ 
		};

	};



	gic: interrupt-controller@e8201000 {

		compatible = "arm,cortex-a9-gic";

		#interrupt-cells = <3>;

		#address-cells = <0>;

		interrupt-controller;

		reg = <0xe8201000 0x1000>,

			<0xe8202000 0x1000>;

	};



	i2c0: i2c@fcfee000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		reg = <0xfcfee000 0x44>;

		interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,

			     <0 158 IRQ_TYPE_EDGE_RISING>,

			     <0 159 IRQ_TYPE_EDGE_RISING>,

			     <0 160 IRQ_TYPE_LEVEL_HIGH>,

			     <0 161 IRQ_TYPE_LEVEL_HIGH>,

			     <0 162 IRQ_TYPE_LEVEL_HIGH>,

			     <0 163 IRQ_TYPE_LEVEL_HIGH>,

			     <0 164 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C0>;

		clock-frequency = <100000>;

		status = "disabled";

	};



	i2c1: i2c@fcfee400 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		reg = <0xfcfee400 0x44>;

		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,

			     <0 166 IRQ_TYPE_EDGE_RISING>,

			     <0 167 IRQ_TYPE_EDGE_RISING>,

			     <0 168 IRQ_TYPE_LEVEL_HIGH>,

			     <0 169 IRQ_TYPE_LEVEL_HIGH>,

			     <0 170 IRQ_TYPE_LEVEL_HIGH>,

			     <0 171 IRQ_TYPE_LEVEL_HIGH>,

			     <0 172 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C1>;

		clock-frequency = <100000>;

		status = "disabled";

	};



	i2c2: i2c@fcfee800 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		reg = <0xfcfee800 0x44>;

		interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,

			     <0 174 IRQ_TYPE_EDGE_RISING>,

			     <0 175 IRQ_TYPE_EDGE_RISING>,

			     <0 176 IRQ_TYPE_LEVEL_HIGH>,

			     <0 177 IRQ_TYPE_LEVEL_HIGH>,

			     <0 178 IRQ_TYPE_LEVEL_HIGH>,

			     <0 179 IRQ_TYPE_LEVEL_HIGH>,

			     <0 180 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C2>;

		clock-frequency = <100000>;

		status = "disabled";

	};



	i2c3: i2c@fcfeec00 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		reg = <0xfcfeec00 0x44>;

		interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,

			     <0 182 IRQ_TYPE_EDGE_RISING>,

			     <0 183 IRQ_TYPE_EDGE_RISING>,

			     <0 184 IRQ_TYPE_LEVEL_HIGH>,

			     <0 185 IRQ_TYPE_LEVEL_HIGH>,

			     <0 186 IRQ_TYPE_LEVEL_HIGH>,

			     <0 187 IRQ_TYPE_LEVEL_HIGH>,

			     <0 188 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C3>;

		clock-frequency = <100000>;

		status = "disabled";

	};



	mtu2: timer@fcff0000 {

		compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";

		reg = <0xfcff0000 0x400>;

		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "tgi0a";

		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;

		clock-names = "fck";

		status = "disabled";

	};



	scif0: serial@e8007000 {

		compatible = "renesas,scif-r7s72100", "renesas,scif";

		reg = <0xe8007000 64>;
@@ -404,4 +313,95 @@ 
		#size-cells = <0>;

		status = "disabled";

	};



	gic: interrupt-controller@e8201000 {

		compatible = "arm,cortex-a9-gic";

		#interrupt-cells = <3>;

		#address-cells = <0>;

		interrupt-controller;

		reg = <0xe8201000 0x1000>,

			<0xe8202000 0x1000>;

	};



	i2c0: i2c@fcfee000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		reg = <0xfcfee000 0x44>;

		interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,

			     <0 158 IRQ_TYPE_EDGE_RISING>,

			     <0 159 IRQ_TYPE_EDGE_RISING>,

			     <0 160 IRQ_TYPE_LEVEL_HIGH>,

			     <0 161 IRQ_TYPE_LEVEL_HIGH>,

			     <0 162 IRQ_TYPE_LEVEL_HIGH>,

			     <0 163 IRQ_TYPE_LEVEL_HIGH>,

			     <0 164 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C0>;

		clock-frequency = <100000>;

		status = "disabled";

	};



	i2c1: i2c@fcfee400 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		reg = <0xfcfee400 0x44>;

		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,

			     <0 166 IRQ_TYPE_EDGE_RISING>,

			     <0 167 IRQ_TYPE_EDGE_RISING>,

			     <0 168 IRQ_TYPE_LEVEL_HIGH>,

			     <0 169 IRQ_TYPE_LEVEL_HIGH>,

			     <0 170 IRQ_TYPE_LEVEL_HIGH>,

			     <0 171 IRQ_TYPE_LEVEL_HIGH>,

			     <0 172 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C1>;

		clock-frequency = <100000>;

		status = "disabled";

	};



	i2c2: i2c@fcfee800 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		reg = <0xfcfee800 0x44>;

		interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,

			     <0 174 IRQ_TYPE_EDGE_RISING>,

			     <0 175 IRQ_TYPE_EDGE_RISING>,

			     <0 176 IRQ_TYPE_LEVEL_HIGH>,

			     <0 177 IRQ_TYPE_LEVEL_HIGH>,

			     <0 178 IRQ_TYPE_LEVEL_HIGH>,

			     <0 179 IRQ_TYPE_LEVEL_HIGH>,

			     <0 180 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C2>;

		clock-frequency = <100000>;

		status = "disabled";

	};



	i2c3: i2c@fcfeec00 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";

		reg = <0xfcfeec00 0x44>;

		interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,

			     <0 182 IRQ_TYPE_EDGE_RISING>,

			     <0 183 IRQ_TYPE_EDGE_RISING>,

			     <0 184 IRQ_TYPE_LEVEL_HIGH>,

			     <0 185 IRQ_TYPE_LEVEL_HIGH>,

			     <0 186 IRQ_TYPE_LEVEL_HIGH>,

			     <0 187 IRQ_TYPE_LEVEL_HIGH>,

			     <0 188 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C3>;

		clock-frequency = <100000>;

		status = "disabled";

	};



	mtu2: timer@fcff0000 {

		compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";

		reg = <0xfcff0000 0x400>;

		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "tgi0a";

		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;

		clock-names = "fck";

		status = "disabled";

	};

};