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Commit 4d555630 authored by Sonic Zhang's avatar Sonic Zhang Committed by Bryan Wu
Browse files

[Blackfin] arch: Update anomaly list. 



Signed-off-by: default avatarSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent 18628e43

include/asm-blackfin/mach-bf527/anomaly.h

+65 −15
Original line number Diff line number Diff line
@@ -2,12 +2,12 @@ 
 * File: include/asm-blackfin/mach-bf527/anomaly.h

 * Bugs: Enter bugs at http://blackfin.uclinux.org/

 *

 * Copyright (C) 2004-2007 Analog Devices Inc.

 * Copyright (C) 2004-2008 Analog Devices Inc.

 * Licensed under the GPL-2 or later.

 */



/* This file shoule be up to date with:

 *  - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List

 *  - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List

 */



#ifndef _MACH_ANOMALY_H_
@@ -15,35 +15,85 @@ 


/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */

#define ANOMALY_05000074 (1)

/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */

#define ANOMALY_05000119 (1)

/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */

#define ANOMALY_05000122 (1)

/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */

#define ANOMALY_05000245 (1)

/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */

#define ANOMALY_05000265 (1)

/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */

#define ANOMALY_05000301 (1)

/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */

#define ANOMALY_05000312 (1)

/* Incorrect Access of OTP_STATUS During otp_write() Function */

#define ANOMALY_05000328 (1)

/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */

#define ANOMALY_05000337 (1)

/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */

/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */

#define ANOMALY_05000341 (1)

/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */

#define ANOMALY_05000342 (1)

/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */

/* USB Calibration Value Is Not Initialized */

#define ANOMALY_05000346 (1)

/* Preboot Routine Incorrectly Alters Reset Value of USB Register */

#define ANOMALY_05000347 (1)

/* Security Features Are Not Functional */

#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)

/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */

#define ANOMALY_05000355 (1)

/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */

#define ANOMALY_05000357 (1)

/* Incorrect Revision Number in DSPID Register */

#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)

/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */

#define ANOMALY_05000366 (1)

/* New Feature: Higher Default CCLK Rate */

#define ANOMALY_05000368 (1)

/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */

#define ANOMALY_05000371 (1)

/* Authentication Fails To Initiate */

#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)

/* Data Read From L3 Memory by USB DMA May be Corrupted */

#define ANOMALY_05000380 (1)

/* USB Full-speed Mode not Fully Tested */

#define ANOMALY_05000381 (1)

/* New Feature: Boot from OTP Memory */

#define ANOMALY_05000385 (1)

/* New Feature: bfrom_SysControl() Routine */

#define ANOMALY_05000386 (1)

/* New Feature: Programmable Preboot Settings */

#define ANOMALY_05000387 (1)

/* Reset Vector Must Not Be in SDRAM Memory Space */

#define ANOMALY_05000389 (1)

/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */

#define ANOMALY_05000392 (1)

/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */

#define ANOMALY_05000393 (1)

/* New Feature: Log Buffer Functionality */

#define ANOMALY_05000394 (1)

/* New Feature: Hook Routine Functionality */

#define ANOMALY_05000395 (1)

/* New Feature: Header Indirect Bit */

#define ANOMALY_05000396 (1)

/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */

#define ANOMALY_05000397 (1)

/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */

#define ANOMALY_05000398 (1)

/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */

#define ANOMALY_05000399 (1)

/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */

#define ANOMALY_05000401 (1)



/* Anomalies that don't exist on this proc */

#define ANOMALY_05000323 (0)

#define ANOMALY_05000244 (0)

#define ANOMALY_05000198 (0)

#define ANOMALY_05000125 (0)

#define ANOMALY_05000158 (0)

#define ANOMALY_05000273 (0)

#define ANOMALY_05000183 (0)

#define ANOMALY_05000198 (0)

#define ANOMALY_05000230 (0)

#define ANOMALY_05000244 (0)

#define ANOMALY_05000261 (0)

#define ANOMALY_05000263 (0)

#define ANOMALY_05000266 (0)

#define ANOMALY_05000273 (0)

#define ANOMALY_05000311 (0)

#define ANOMALY_05000230 (0)

#define ANOMALY_05000312 (0)

#define ANOMALY_05000323 (0)

#define ANOMALY_05000363 (0)



#endif

include/asm-blackfin/mach-bf533/anomaly.h

+9 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 
 */



/* This file shoule be up to date with:

 *  - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List

 *  - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List

 */



#ifndef _MACH_ANOMALY_H_
@@ -251,10 +251,18 @@ 
#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)

/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */

#define ANOMALY_05000357 (1)

/* UART Break Signal Issues */

#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)

/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */

#define ANOMALY_05000366 (1)

/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */

#define ANOMALY_05000371 (1)

/* PPI Does Not Start Properly In Specific Mode */

#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)

/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */

#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)

/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */

#define ANOMALY_05000403 (1)



/* Anomalies that don't exist on this proc */

#define ANOMALY_05000266 (0)

include/asm-blackfin/mach-bf537/anomaly.h

+16 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 
 */



/* This file shoule be up to date with:

 *  - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List

 *  - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List

 */



#ifndef _MACH_ANOMALY_H_
@@ -132,10 +132,24 @@ 
#define ANOMALY_05000322 (1)

/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */

#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)

/* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */

#define ANOMALY_05000350 (__SILICON_REVISION__ < 3)

/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */

#define ANOMALY_05000355 (1)

/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */

#define ANOMALY_05000357 (1)

/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */

#define ANOMALY_05000359 (1)

/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */

#define ANOMALY_05000366 (1)

/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */

#define ANOMALY_05000371 (1)

/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */

#define ANOMALY_05000402 (__SILICON_REVISION__ >= 3)

/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */

#define ANOMALY_05000403 (1)







/* Anomalies that don't exist on this proc */

#define ANOMALY_05000125 (0)
@@ -146,5 +160,6 @@ 
#define ANOMALY_05000266 (0)

#define ANOMALY_05000311 (0)

#define ANOMALY_05000323 (0)

#define ANOMALY_05000363 (0)



#endif

include/asm-blackfin/mach-bf548/anomaly.h

+1 −0
Original line number Diff line number Diff line
@@ -93,5 +93,6 @@ 
#define ANOMALY_05000273 (0)

#define ANOMALY_05000311 (0)

#define ANOMALY_05000323 (0)

#define ANOMALY_05000363 (0)



#endif

include/asm-blackfin/mach-bf561/anomaly.h

+5 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 
 */



/* This file shoule be up to date with:

 *  - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List

 *  - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List

 */



#ifndef _MACH_ANOMALY_H_
@@ -256,10 +256,14 @@ 
#define ANOMALY_05000357 (1)

/* Conflicting Column Address Widths Causes SDRAM Errors */

#define ANOMALY_05000362 (1)

/* UART Break Signal Issues */

#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)

/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */

#define ANOMALY_05000366 (1)

/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */

#define ANOMALY_05000371 (1)

/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */

#define ANOMALY_05000403 (1)



/* Anomalies that don't exist on this proc */

#define ANOMALY_05000158 (0)