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Commit 4cc3daaf authored by Will Deacon's avatar Will Deacon
Browse files

ARM: tlbflush: remove ARMv3 support 



We no longer support any ARMv3 platforms, so remove the old tlbflushing
code.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 8bb96604

arch/arm/include/asm/tlbflush.h

+2 −9
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ 


#include <asm/glue.h>



#define TLB_V3_PAGE	(1 << 0)

#define TLB_V4_U_PAGE	(1 << 1)

#define TLB_V4_D_PAGE	(1 << 2)

#define TLB_V4_I_PAGE	(1 << 3)
@@ -22,7 +21,6 @@ 
#define TLB_V6_D_PAGE	(1 << 5)

#define TLB_V6_I_PAGE	(1 << 6)



#define TLB_V3_FULL	(1 << 8)

#define TLB_V4_U_FULL	(1 << 9)

#define TLB_V4_D_FULL	(1 << 10)

#define TLB_V4_I_FULL	(1 << 11)
@@ -52,7 +50,6 @@ 
 *	=============

 *

 *	We have the following to choose from:

 *	  v3    - ARMv3

 *	  v4    - ARMv4 without write buffer

 *	  v4wb  - ARMv4 with write buffer without I TLB flush entry instruction

 *	  v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
@@ -330,7 +327,6 @@ static inline void local_flush_tlb_all(void) 
	if (tlb_flag(TLB_WB))

		dsb();



	tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);

	tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero);

	tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero);

	tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero);
@@ -351,9 +347,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) 
	if (tlb_flag(TLB_WB))

		dsb();



	if (possible_tlb_flags & (TLB_V3_FULL|TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {

	if (possible_tlb_flags & (TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {

		if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {

			tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);

			tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);

			tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);

			tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
@@ -385,9 +380,8 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) 
	if (tlb_flag(TLB_WB))

		dsb();



	if (possible_tlb_flags & (TLB_V3_PAGE|TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&

	if (possible_tlb_flags & (TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&

	    cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {

		tlb_op(TLB_V3_PAGE, "c6, c0, 0", uaddr);

		tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);

		tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);

		tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);
@@ -418,7 +412,6 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) 
	if (tlb_flag(TLB_WB))

		dsb();



	tlb_op(TLB_V3_PAGE, "c6, c0, 0", kaddr);

	tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);

	tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);

	tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);