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Commit 4bb0d3ec authored by Zachary Amsden's avatar Zachary Amsden Committed by Linus Torvalds
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[PATCH] i386: inline asm cleanup 



i386 Inline asm cleanup.  Use cr/dr accessor functions.

Also, a potential bugfix.  Also, some CR accessors really should be volatile.
Reads from CR0 (numeric state may change in an exception handler), writes to
CR4 (flipping CR4.TSD) and reads from CR2 (page fault) prevent instruction
re-ordering.  I did not add memory clobber to CR3 / CR4 / CR0 updates, as it
was not there to begin with, and in no case should kernel memory be clobbered,
except when doing a TLB flush, which already has memory clobber.

I noticed that page invalidation does not have a memory clobber.  I can't find
a bug as a result, but there is definitely a potential for a bug here:

#define __flush_tlb_single(addr) \
	__asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))

Signed-off-by: default avatarZachary Amsden <zach@vmware.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 2a0694d1

arch/i386/kernel/cpu/common.c

+6 −6
Original line number Diff line number Diff line
@@ -642,12 +642,12 @@ void __devinit cpu_init(void) 
	asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");



	/* Clear all 6 debug registers: */



#define CD(register) set_debugreg(0, register)



	CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);



#undef CD

	set_debugreg(0, 0);

	set_debugreg(0, 1);

	set_debugreg(0, 2);

	set_debugreg(0, 3);

	set_debugreg(0, 6);

	set_debugreg(0, 7);



	/*

	 * Force FPU initialization:

arch/i386/kernel/cpu/cpufreq/longhaul.c

+3 −9
Original line number Diff line number Diff line
@@ -64,8 +64,6 @@ static int dont_scale_voltage; 
#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)





#define __hlt()     __asm__ __volatile__("hlt": : :"memory")



/* Clock ratios multiplied by 10 */

static int clock_ratio[32];

static int eblcr_table[32];
@@ -168,11 +166,9 @@ static void do_powersaver(union msr_longhaul *longhaul, 
	outb(0xFE,0x21);	/* TMR0 only */

	outb(0xFF,0x80);	/* delay */



	local_irq_enable();



	__hlt();

	safe_halt();

	wrmsrl(MSR_VIA_LONGHAUL, longhaul->val);

	__hlt();

	halt();



	local_irq_disable();
@@ -251,9 +247,7 @@ static void longhaul_setstate(unsigned int clock_ratio_index) 
		bcr2.bits.CLOCKMUL = clock_ratio_index;

		local_irq_disable();

		wrmsrl (MSR_VIA_BCR2, bcr2.val);

		local_irq_enable();



		__hlt();

		safe_halt();



		/* Disable software clock multiplier */

		rdmsrl (MSR_VIA_BCR2, bcr2.val);

arch/i386/kernel/cpu/cyrix.c

+1 −5
Original line number Diff line number Diff line
@@ -132,11 +132,7 @@ static void __init set_cx86_memwb(void) 
	setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);

	/* set 'Not Write-through' */

	cr0 = 0x20000000;

	__asm__("movl %%cr0,%%eax\n\t"

		"orl %0,%%eax\n\t"

		"movl %%eax,%%cr0\n"

		: : "r" (cr0)

		:"ax");

	write_cr0(read_cr0() | cr0);

	/* CCR2 bit 2: lock NW bit and set WT1 */

	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 );

}

arch/i386/kernel/efi.c

+2 −2
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ static void efi_call_phys_prelog(void) 
	 * directory. If I have PSE, I just need to duplicate one entry in

	 * page directory.

	 */

	__asm__ __volatile__("movl %%cr4, %0":"=r"(cr4));

	cr4 = read_cr4();



	if (cr4 & X86_CR4_PSE) {

		efi_bak_pg_dir_pointer[0].pgd =
@@ -115,7 +115,7 @@ static void efi_call_phys_epilog(void) 
	cpu_gdt_descr[0].address =

		(unsigned long) __va(cpu_gdt_descr[0].address);

	__asm__ __volatile__("lgdt %0":"=m"(cpu_gdt_descr));

	__asm__ __volatile__("movl %%cr4, %0":"=r"(cr4));

	cr4 = read_cr4();



	if (cr4 & X86_CR4_PSE) {

		swapper_pg_dir[pgd_index(0)].pgd =

arch/i386/kernel/machine_kexec.c

+1 −7
Original line number Diff line number Diff line
@@ -17,13 +17,7 @@ 
#include <asm/apic.h>

#include <asm/cpufeature.h>

#include <asm/desc.h>



static inline unsigned long read_cr3(void)

{

	unsigned long cr3;

	asm volatile("movl %%cr3,%0": "=r"(cr3));

	return cr3;

}

#include <asm/system.h>



#define PAGE_ALIGNED __attribute__ ((__aligned__(PAGE_SIZE)))