Commit 4b9b7b3a authored Jul 12, 2016 by Sergei Shtylyov Committed by Simon Horman Jul 15, 2016

ARM: dts: r8a7792: add PLL1 divided by 2 clock



Despite the fact that QSPI clock has PLL1/VCOx1/4 clock as a parent, the
latter hasn't been added to the R8A7792 device tree. This patch corrects
that oversight.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

parent 8fd763c7

arch/arm/boot/dts/r8a7792.dtsi

+7 −0

Original line number	Diff line number	Diff line
		@@ -284,6 +284,13 @@
		};

		/* Fixed factor clocks */
		pll1_div2_clk: pll1_div2 {
		compatible = "fixed-factor-clock";
		clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
		#clock-cells = <0>;
		clock-div = <2>;
		clock-mult = <1>;
		};
		zs_clk: zs {
		compatible = "fixed-factor-clock";
		clocks = <&cpg_clocks R8A7792_CLK_PLL1>;