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Commit 4b40e592 authored by Christian König's avatar Christian König Committed by Alex Deucher
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drm/radeon/uvd: lower msg&fb buffer requirements on UVD3 



Starting with UVD3 message and feedback buffers have their
own 256MB segment, so no need to force them into VRAM any more.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4a1132a0

drivers/gpu/drm/radeon/radeon_cs.c

+2 −1
Original line number Diff line number Diff line
@@ -85,8 +85,9 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) 
		   VRAM, also but everything into VRAM on AGP cards to avoid

		   image corruptions */

		if (p->ring == R600_RING_TYPE_UVD_INDEX &&

		    p->rdev->family < CHIP_PALM &&

		    (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {

			/* TODO: is this still needed for NI+ ? */



			p->relocs[i].lobj.domain =

				RADEON_GEM_DOMAIN_VRAM;

drivers/gpu/drm/radeon/radeon_uvd.c

+1 −2
Original line number Diff line number Diff line
@@ -476,8 +476,7 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, 
		return -EINVAL;

	}



	/* TODO: is this still necessary on NI+ ? */

	if ((cmd == 0 || cmd == 0x3) &&

	if (p->rdev->family < CHIP_PALM && (cmd == 0 || cmd == 0x3) &&

	    (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {

		DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",

			  start, end);

drivers/gpu/drm/radeon/uvd_v1_0.c

+2 −2
Original line number Diff line number Diff line
@@ -212,8 +212,8 @@ int uvd_v1_0_start(struct radeon_device *rdev) 
	/* enable VCPU clock */

	WREG32(UVD_VCPU_CNTL,  1 << 9);



	/* enable UMC */

	WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));

	/* enable UMC and NC0 */

	WREG32_P(UVD_LMI_CTRL2, 1 << 13, ~((1 << 8) | (1 << 13)));



	/* boot up the VCPU */

	WREG32(UVD_SOFT_RESET, 0);