Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 49afdeb6 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
Browse files

[TG3]: Use lower DMA watermark for 5703. 



Set DMA read watermark to 4 on 5703 in PCIX mode.  This is needed to
prevent some tx timeouts.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 436f1379

drivers/net/tg3.c

+7 −1
Original line number Diff line number Diff line
@@ -11314,6 +11314,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp) 
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||

		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {

			u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);

			u32 read_water = 0x7;



			/* If the 5704 is behind the EPB bridge, we can

			 * do the less restrictive ONE_DMA workaround for
@@ -11325,8 +11326,13 @@ static int __devinit tg3_test_dma(struct tg3 *tp) 
			else if (ccval == 0x6 || ccval == 0x7)

				tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;



			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)

				read_water = 4;

			/* Set bit 23 to enable PCIX hw bug fix */

			tp->dma_rwctrl |= 0x009f0000;

			tp->dma_rwctrl |=

				(read_water << DMA_RWCTRL_READ_WATER_SHIFT) |

				(0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |

				(1 << 23);

		} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {

			/* 5780 always in PCIX mode */

			tp->dma_rwctrl |= 0x00144000;