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Commit 49677901 authored by Priit Laes's avatar Priit Laes Committed by Eric Anholt
Browse files

drm/i915: Rename FBC_C3_IDLE to FBC_CTL_C3_IDLE to match other registers 



Signed-off-by: default avatarPriit Laes <plaes@plaes.org>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 5d939162

drivers/gpu/drm/i915/i915_reg.h

+1 −1
Original line number Diff line number Diff line
@@ -366,7 +366,7 @@ 
#define   FBC_CTL_PERIODIC	(1<<30)

#define   FBC_CTL_INTERVAL_SHIFT (16)

#define   FBC_CTL_UNCOMPRESSIBLE (1<<14)

#define   FBC_C3_IDLE		(1<<13)

#define   FBC_CTL_C3_IDLE	(1<<13)

#define   FBC_CTL_STRIDE_SHIFT	(5)

#define   FBC_CTL_FENCENO	(1<<0)

#define FBC_COMMAND		0x0320c

drivers/gpu/drm/i915/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -1032,7 +1032,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
	/* enable it... */

	fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;

	if (IS_I945GM(dev))

		fbc_ctl |= FBC_C3_IDLE; /* 945 needs special SR handling */

		fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */

	fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;

	fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;

	if (obj_priv->tiling_mode != I915_TILING_NONE)