Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 48299f95 authored by David Zhang's avatar David Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: Add Fiji DID 0x7300 common support 



Signed-off-by: default avatarDavid Zhang <david1.zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
parent 41548ef7

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −0
Original line number Diff line number Diff line
@@ -55,6 +55,7 @@ static const char *amdgpu_asic_name[] = { 
	"MULLINS",

	"TOPAZ",

	"TONGA",

	"FIJI",

	"CARRIZO",

	"LAST",

};
@@ -1160,6 +1161,7 @@ static int amdgpu_early_init(struct amdgpu_device *adev) 
	switch (adev->asic_type) {

	case CHIP_TOPAZ:

	case CHIP_TONGA:

	case CHIP_FIJI:

	case CHIP_CARRIZO:

		if (adev->asic_type == CHIP_CARRIZO)

			adev->family = AMDGPU_FAMILY_CZ;

drivers/gpu/drm/amd/amdgpu/vi.c

+34 −0
Original line number Diff line number Diff line
@@ -203,6 +203,17 @@ static const u32 tonga_mgcg_cgcg_init[] = 
	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,

};



static const u32 fiji_mgcg_cgcg_init[] =

{

	mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,

	mmPCIE_INDEX, 0xffffffff, 0x0140001c,

	mmPCIE_DATA, 0x000f0000, 0x00000000,

	mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,

	mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,

	mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,

	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,

};



static const u32 iceland_mgcg_cgcg_init[] =

{

	mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
@@ -232,6 +243,11 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) 
						 iceland_mgcg_cgcg_init,

						 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));

		break;

	case CHIP_FIJI:

		amdgpu_program_register_sequence(adev,

						 fiji_mgcg_cgcg_init,

						 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));

		break;

	case CHIP_TONGA:

		amdgpu_program_register_sequence(adev,

						 tonga_mgcg_cgcg_init,
@@ -469,6 +485,7 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, 
		asic_register_table = tonga_allowed_read_registers;

		size = ARRAY_SIZE(tonga_allowed_read_registers);

		break;

	case CHIP_FIJI:

	case CHIP_TONGA:

	case CHIP_CARRIZO:

		asic_register_table = cz_allowed_read_registers;
@@ -1147,6 +1164,18 @@ static const struct amdgpu_ip_block_version tonga_ip_blocks[] = 
	},

};



static const struct amdgpu_ip_block_version fiji_ip_blocks[] =

{

	/* ORDER MATTERS! */

	{

		.type = AMD_IP_BLOCK_TYPE_COMMON,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &vi_common_ip_funcs,

	}

};



static const struct amdgpu_ip_block_version cz_ip_blocks[] =

{

	/* ORDER MATTERS! */
@@ -1222,6 +1251,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) 
		adev->ip_blocks = topaz_ip_blocks;

		adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);

		break;

	case CHIP_FIJI:

		adev->ip_blocks = fiji_ip_blocks;

		adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);

		break;

	case CHIP_TONGA:

		adev->ip_blocks = tonga_ip_blocks;

		adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
@@ -1299,6 +1332,7 @@ static int vi_common_early_init(void *handle) 
		if (amdgpu_smc_load_fw && smc_enabled)

			adev->firmware.smu_load = true;

		break;

	case CHIP_FIJI:

	case CHIP_TONGA:

		adev->has_uvd = true;

		adev->cg_flags = 0;

drivers/gpu/drm/amd/include/amd_shared.h

+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ enum amd_asic_type { 
	CHIP_MULLINS,

	CHIP_TOPAZ,

	CHIP_TONGA,

	CHIP_FIJI,

	CHIP_CARRIZO,

	CHIP_LAST,

};