Commit 48004881 authored Nov 07, 2016 by Chris Wilson Committed by Jani Nikula Nov 11, 2016

drm/i915: Mark CPU cache as dirty when used for rendering

On LLC, or even snooped, machines rendering via the GPU ends up in the CPU
cache. This cacheline dirt also needs to be flushed to main memory when
moving to an incoherent domain, such as the display's scanout engine.
Mostly, this happens because either the object is marked as dirty from
its first use or is avoided by setting the object into the display
domain from the start.

v2: Treat WT as not requiring a clflush prior to use on the display
engine as well.

Fixes: 0f71979a ("drm/i915: Performed deferred clflush inside set-cache-level")
References: https://bugs.freedesktop.org/show_bug.cgi?id=95414


Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: <stable@vger.kernel.org> # v4.0+
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107165204.7008-1-chris@chris-wilson.co.uk


(cherry picked from commit 7aa6ca61ee5546d74b76610894924cdb0d4a1af0)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

parent 54905ab5

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1281,6 +1281,12 @@ i915_gem_validate_context(struct drm_device dev, struct drm_file file,
	return ctx;		return ctx;
	}		}

			static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
			{
			return !(obj->cache_level == I915_CACHE_NONE \|\|
			obj->cache_level == I915_CACHE_WT);
			}

	void i915_vma_move_to_active(struct i915_vma *vma,		void i915_vma_move_to_active(struct i915_vma *vma,
	struct drm_i915_gem_request *req,		struct drm_i915_gem_request *req,
	unsigned int flags)		unsigned int flags)
	@@ -1311,6 +1317,8 @@ void i915_vma_move_to_active(struct i915_vma *vma,

	/* update for the implicit flush after a batch */		/* update for the implicit flush after a batch */
	obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;		obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
			if (!obj->cache_dirty && gpu_write_needs_clflush(obj))
			obj->cache_dirty = true;
	}		}

	if (flags & EXEC_OBJECT_NEEDS_FENCE)		if (flags & EXEC_OBJECT_NEEDS_FENCE)