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Commit 475d92fc authored by Will Deacon's avatar Will Deacon Committed by Russell King
Browse files

ARM: 6416/1: errata: faulty hazard checking in the Store Buffer may lead to data corruption 



On the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption
can occur under very rare conditions due to a store buffer optimisation.

This workaround sets a bit in the diagnostic register of the Cortex-A9,
disabling the optimisation and preventing the problem from occurring.

Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent c6ea21e3

arch/arm/Kconfig

+14 −0
Original line number Diff line number Diff line
@@ -1101,6 +1101,20 @@ config ARM_ERRATA_720789 
	  invalidated are not, resulting in an incoherency in the system page

	  tables. The workaround changes the TLB flushing routines to invalidate

	  entries regardless of the ASID.



config ARM_ERRATA_743622

	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"

	depends on CPU_V7

	help

	  This option enables the workaround for the 743622 Cortex-A9

	  (r2p0..r2p2) erratum. Under very rare conditions, a faulty

	  optimisation in the Cortex-A9 Store Buffer may lead to data

	  corruption. This workaround sets a specific bit in the diagnostic

	  register of the Cortex-A9 which disables the Store Buffer

	  optimisation, preventing the defect from occurring. This has no

	  visible impact on the overall performance or power consumption of the

	  processor.



endmenu



source "arch/arm/common/Kconfig"

arch/arm/mm/proc-v7.S

+8 −0
Original line number Diff line number Diff line
@@ -253,6 +253,14 @@ __v7_setup: 
	orreq	r10, r10, #1 << 22		@ set bit #22

	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register

#endif

#ifdef CONFIG_ARM_ERRATA_743622

	teq	r6, #0x20			@ present in r2p0

	teqne	r6, #0x21			@ present in r2p1

	teqne	r6, #0x22			@ present in r2p2

	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register

	orreq	r10, r10, #1 << 6		@ set bit #6

	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register

#endif



3:	mov	r10, #0

#ifdef HARVARD_CACHE