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Commit 45eb5168 authored by David S. Miller's avatar David S. Miller
Browse files

Merge tag 'wireless-drivers-next-for-davem-2015-04-01' of... 

Merge tag 'wireless-drivers-next-for-davem-2015-04-01' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next



Kalle Valo says:

====================
Major changes:

ath9k:

* add Active Interference Cancellation, a method implemented in the HW
  to counter WLAN RX > sensitivity degradation when BT is transmitting
  at the same time. This feature is supported by cards like WB222
  based on AR9462.

iwlwifi:

* Location Aware Regulatory was added by Arik
* 8000 device family work
* update to the BT Coex firmware API

brmcfmac:

* add new BCM43455 and BCM43457 SDIO device support
* add new BCM43430 SDIO device support

wil6210:

* take care of AP bridging
* fix NAPI behavior
* found approach to achieve 4*n+2 alignment of Rx frames

rt2x00:

* add new rt2800usb device DWA 130

rtlwifi:

* add USB ID for D-Link DWA-131
* add USB ID ASUS N10 WiFi dongle

mwifiex:

* throughput enhancements
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents b9600d2d 9374e7d2

drivers/bcma/Kconfig

+3 −3
Original line number Diff line number Diff line 
config BCMA_POSSIBLE

	bool

	depends on HAS_IOMEM && HAS_DMA && PCI

	depends on HAS_IOMEM && HAS_DMA

	default y



menu "Broadcom specific AMBA"
@@ -45,9 +45,9 @@ config BCMA_HOST_SOC 


	  If unsure, say N



# TODO: make it depend on PCI when ready

config BCMA_DRIVER_PCI

	bool

	bool "BCMA Broadcom PCI core driver"

	depends on BCMA && PCI

	default y

	help

	  BCMA bus may have many versions of PCIe core. This driver

drivers/bcma/bcma_private.h

+20 −0
Original line number Diff line number Diff line
@@ -106,15 +106,35 @@ static inline void __exit bcma_host_soc_unregister_driver(void) 
#endif /* CONFIG_BCMA_HOST_SOC && CONFIG_OF */



/* driver_pci.c */

#ifdef CONFIG_BCMA_DRIVER_PCI

u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);

void bcma_core_pci_early_init(struct bcma_drv_pci *pc);

void bcma_core_pci_init(struct bcma_drv_pci *pc);

void bcma_core_pci_up(struct bcma_drv_pci *pc);

void bcma_core_pci_down(struct bcma_drv_pci *pc);

#else

static inline void bcma_core_pci_early_init(struct bcma_drv_pci *pc)

{

	WARN_ON(pc->core->bus->hosttype == BCMA_HOSTTYPE_PCI);

}

static inline void bcma_core_pci_init(struct bcma_drv_pci *pc)

{

	/* Initialization is required for PCI hosted bus */

	WARN_ON(pc->core->bus->hosttype == BCMA_HOSTTYPE_PCI);

}

#endif



/* driver_pcie2.c */

#ifdef CONFIG_BCMA_DRIVER_PCI

void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);

void bcma_core_pcie2_up(struct bcma_drv_pcie2 *pcie2);

#else

static inline void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)

{

	/* Initialization is required for PCI hosted bus */

	WARN_ON(pcie2->core->bus->hosttype == BCMA_HOSTTYPE_PCI);

}

#endif



extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);

drivers/bcma/driver_gpio.c

+15 −8
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ 


#include "bcma_private.h"



#define BCMA_GPIO_MAX_PINS	32



static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)

{

	return container_of(chip, struct bcma_drv_cc, gpio);
@@ -204,6 +206,7 @@ static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc) 


int bcma_gpio_init(struct bcma_drv_cc *cc)

{

	struct bcma_bus *bus = cc->core->bus;

	struct gpio_chip *chip = &cc->gpio;

	int err;
@@ -222,7 +225,7 @@ int bcma_gpio_init(struct bcma_drv_cc *cc) 
	if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)

		chip->of_node	= cc->core->dev.of_node;

#endif

	switch (cc->core->bus->chipinfo.id) {

	switch (bus->chipinfo.id) {

	case BCMA_CHIP_ID_BCM5357:

	case BCMA_CHIP_ID_BCM53572:

		chip->ngpio	= 32;
@@ -231,13 +234,17 @@ int bcma_gpio_init(struct bcma_drv_cc *cc) 
		chip->ngpio	= 16;

	}



	/* There is just one SoC in one device and its GPIO addresses should be

	 * deterministic to address them more easily. The other buses could get

	 * a random base number. */

	if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)

		chip->base		= 0;

	else

	/*

	 * On MIPS we register GPIO devices (LEDs, buttons) using absolute GPIO

	 * pin numbers. We don't have Device Tree there and we can't really use

	 * relative (per chip) numbers.

	 * So let's use predictable base for BCM47XX and "random" for all other.

	 */

#if IS_BUILTIN(CONFIG_BCM47XX)

	chip->base		= bus->num * BCMA_GPIO_MAX_PINS;

#else

	chip->base		= -1;

#endif



	err = bcma_gpio_irq_domain_init(cc);

	if (err)

drivers/bcma/driver_pci.c

+0 −33
Original line number Diff line number Diff line
@@ -282,39 +282,6 @@ void bcma_core_pci_power_save(struct bcma_bus *bus, bool up) 
}

EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);



int bcma_core_pci_irq_ctl(struct bcma_bus *bus, struct bcma_device *core,

			  bool enable)

{

	struct pci_dev *pdev;

	u32 coremask, tmp;

	int err = 0;



	if (bus->hosttype != BCMA_HOSTTYPE_PCI) {

		/* This bcma device is not on a PCI host-bus. So the IRQs are

		 * not routed through the PCI core.

		 * So we must not enable routing through the PCI core. */

		goto out;

	}



	pdev = bus->host_pci;



	err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);

	if (err)

		goto out;



	coremask = BIT(core->core_index) << 8;

	if (enable)

		tmp |= coremask;

	else

		tmp &= ~coremask;



	err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);



out:

	return err;

}

EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);



static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)

{

	u32 w;

drivers/bcma/host_pci.c

+34 −0
Original line number Diff line number Diff line
@@ -351,3 +351,37 @@ void bcma_host_pci_down(struct bcma_bus *bus) 
		bcma_core_pci_down(&bus->drv_pci[0]);

}

EXPORT_SYMBOL_GPL(bcma_host_pci_down);



/* See also si_pci_setup */

int bcma_host_pci_irq_ctl(struct bcma_bus *bus, struct bcma_device *core,

			  bool enable)

{

	struct pci_dev *pdev;

	u32 coremask, tmp;

	int err = 0;



	if (bus->hosttype != BCMA_HOSTTYPE_PCI) {

		/* This bcma device is not on a PCI host-bus. So the IRQs are

		 * not routed through the PCI core.

		 * So we must not enable routing through the PCI core. */

		goto out;

	}



	pdev = bus->host_pci;



	err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);

	if (err)

		goto out;



	coremask = BIT(core->core_index) << 8;

	if (enable)

		tmp |= coremask;

	else

		tmp &= ~coremask;



	err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);



out:

	return err;

}

EXPORT_SYMBOL_GPL(bcma_host_pci_irq_ctl);