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Commit 44f37d1f authored by Chon Ming Lee's avatar Chon Ming Lee Committed by Daniel Vetter
Browse files

drm/i915/chv: Pipe select change for DP and HDMI 



With additional of pipe C, current 1 bit registers for pipe select
for HDMI and DP are no longer able to gather for 3 pipes. As a result,
new bits location in the same registers are added.

For HDMI, VLV uses bit 30, CHV uses bit 24-25.

For DP, VLV uses bit 30, CHV uses bit 16-17.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarChon Ming Lee <chon.ming.lee@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e4a1d846

drivers/gpu/drm/i915/i915_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -2510,6 +2510,10 @@ enum punit_power_well { 
#define   SDVO_PIPE_SEL_CPT(pipe)		((pipe) << 29)

#define   SDVO_PIPE_SEL_MASK_CPT		(3 << 29)



/* CHV SDVO/HDMI bits: */

#define   SDVO_PIPE_SEL_CHV(pipe)		((pipe) << 24)

#define   SDVO_PIPE_SEL_MASK_CHV		(3 << 24)





/* DVO port control */

#define DVOA			0x61120
@@ -3267,6 +3271,8 @@ enum punit_power_well { 
#define   DP_PORT_EN			(1 << 31)

#define   DP_PIPEB_SELECT		(1 << 30)

#define   DP_PIPE_MASK			(1 << 30)

#define   DP_PIPE_SELECT_CHV(pipe)	((pipe) << 16)

#define   DP_PIPE_MASK_CHV		(3 << 16)



/* Link training mode - select a suitable mode for each stage */

#define   DP_LINK_TRAIN_PAT_1		(0 << 28)

drivers/gpu/drm/i915/intel_display.c

+6 −0
Original line number Diff line number Diff line
@@ -1337,6 +1337,9 @@ static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, 
		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);

		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)

			return false;

	} else if (IS_CHERRYVIEW(dev_priv->dev)) {

		if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))

			return false;

	} else {

		if ((val & DP_PIPE_MASK) != (pipe << 30))

			return false;
@@ -1353,6 +1356,9 @@ static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, 
	if (HAS_PCH_CPT(dev_priv->dev)) {

		if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))

			return false;

	} else if (IS_CHERRYVIEW(dev_priv->dev)) {

		if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))

			return false;

	} else {

		if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))

			return false;

drivers/gpu/drm/i915/intel_dp.c

+6 −2
Original line number Diff line number Diff line
@@ -992,8 +992,12 @@ static void intel_dp_mode_set(struct intel_encoder *encoder) 
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))

			intel_dp->DP |= DP_ENHANCED_FRAMING;



		if (!IS_CHERRYVIEW(dev)) {

			if (crtc->pipe == 1)

				intel_dp->DP |= DP_PIPEB_SELECT;

		} else {

			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);

		}

	} else {

		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

	}

drivers/gpu/drm/i915/intel_hdmi.c

+2 −0
Original line number Diff line number Diff line
@@ -664,6 +664,8 @@ static void intel_hdmi_mode_set(struct intel_encoder *encoder) 


	if (HAS_PCH_CPT(dev))

		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);

	else if (IS_CHERRYVIEW(dev))

		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);

	else

		hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);