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Commit 44d921b2 authored by Kumba's avatar Kumba Committed by Ralf Baechle
Browse files

[MIPS] Treat R14000 like R10000. 



Signed-off-by: default avatarJoshua Kinard <kumba@gentoo.org>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 714bfad6

arch/mips/kernel/cpu-probe.c

+9 −0
Original line number Diff line number Diff line
@@ -433,6 +433,15 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) 
		             MIPS_CPU_LLSC;

		c->tlbsize = 64;

		break;

	case PRID_IMP_R14000:

		c->cputype = CPU_R14000;

		c->isa_level = MIPS_CPU_ISA_IV;

		c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |

		             MIPS_CPU_FPU | MIPS_CPU_32FPR |

			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |

		             MIPS_CPU_LLSC;

		c->tlbsize = 64;

		break;

	}

}

arch/mips/kernel/proc.c

+1 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ static const char *cpu_name[] = { 
	[CPU_R8000]	= "R8000",

	[CPU_R10000]	= "R10000",

	[CPU_R12000]	= "R12000",

	[CPU_R14000]	= "R14000",

	[CPU_R4300]	= "R4300",

	[CPU_R4650]	= "R4650",

	[CPU_R4700]	= "R4700",

arch/mips/mm/c-r4k.c

+4 −0
Original line number Diff line number Diff line
@@ -335,6 +335,7 @@ static inline void local_r4k___flush_cache_all(void * args) 
	case CPU_R4400MC:

	case CPU_R10000:

	case CPU_R12000:

	case CPU_R14000:

		r4k_blast_scache();

	}

}
@@ -833,6 +834,7 @@ static void __init probe_pcache(void) 


	case CPU_R10000:

	case CPU_R12000:

	case CPU_R14000:

		icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));

		c->icache.linesz = 64;

		c->icache.ways = 2;
@@ -986,6 +988,7 @@ static void __init probe_pcache(void) 
		c->dcache.flags |= MIPS_CACHE_PINDEX;

	case CPU_R10000:

	case CPU_R12000:

	case CPU_R14000:

	case CPU_SB1:

		break;

	case CPU_24K:
@@ -1113,6 +1116,7 @@ static void __init setup_scache(void) 


	case CPU_R10000:

	case CPU_R12000:

	case CPU_R14000:

		scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);

		c->scache.linesz = 64 << ((config >> 13) & 1);

		c->scache.ways = 2;

arch/mips/mm/pg-r4k.c

+1 −0
Original line number Diff line number Diff line
@@ -357,6 +357,7 @@ void __init build_clear_page(void) 


		case CPU_R10000:

		case CPU_R12000:

		case CPU_R14000:

			pref_src_mode = Pref_LoadStreamed;

			pref_dst_mode = Pref_StoreStreamed;

			break;

arch/mips/mm/tlbex.c

+1 −0
Original line number Diff line number Diff line
@@ -875,6 +875,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, 


	case CPU_R10000:

	case CPU_R12000:

	case CPU_R14000:

	case CPU_4KC:

	case CPU_SB1:

	case CPU_SB1A: