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Commit 44ae3ab3 authored by Matt Evans's avatar Matt Evans Committed by Benjamin Herrenschmidt
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powerpc: Free up some CPU feature bits by moving out MMU-related features 



Some of the 64bit PPC CPU features are MMU-related, so this patch moves
them to MMU_FTR_ bits.  All cpu_has_feature()-style tests are moved to
mmu_has_feature(), and seven feature bits are freed as a result.

Signed-off-by: default avatarMatt Evans <matt@ozlabs.org>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent eca590f4

arch/powerpc/include/asm/cputable.h

+14 −23
Original line number Original line Diff line number Diff line
@@ -178,23 +178,17 @@ extern const char *powerpc_base_platform; 
#define LONG_ASM_CONST(x)		0

#define LONG_ASM_CONST(x)		0

#endif

#endif





#define CPU_FTR_SLB			LONG_ASM_CONST(0x0000000100000000)



#define CPU_FTR_16M_PAGE		LONG_ASM_CONST(0x0000000200000000)

#define CPU_FTR_TLBIEL			LONG_ASM_CONST(0x0000000400000000)

#define CPU_FTR_HVMODE_206		LONG_ASM_CONST(0x0000000800000000)

#define CPU_FTR_HVMODE_206		LONG_ASM_CONST(0x0000000800000000)

#define CPU_FTR_IABR			LONG_ASM_CONST(0x0000002000000000)

#define CPU_FTR_IABR			LONG_ASM_CONST(0x0000002000000000)

#define CPU_FTR_MMCRA			LONG_ASM_CONST(0x0000004000000000)

#define CPU_FTR_MMCRA			LONG_ASM_CONST(0x0000004000000000)

#define CPU_FTR_CTRL			LONG_ASM_CONST(0x0000008000000000)

#define CPU_FTR_CTRL			LONG_ASM_CONST(0x0000008000000000)

#define CPU_FTR_SMT			LONG_ASM_CONST(0x0000010000000000)

#define CPU_FTR_SMT			LONG_ASM_CONST(0x0000010000000000)

#define CPU_FTR_LOCKLESS_TLBIE		LONG_ASM_CONST(0x0000040000000000)

#define CPU_FTR_CI_LARGE_PAGE		LONG_ASM_CONST(0x0000100000000000)

#define CPU_FTR_PAUSE_ZERO		LONG_ASM_CONST(0x0000200000000000)

#define CPU_FTR_PAUSE_ZERO		LONG_ASM_CONST(0x0000200000000000)

#define CPU_FTR_PURR			LONG_ASM_CONST(0x0000400000000000)

#define CPU_FTR_PURR			LONG_ASM_CONST(0x0000400000000000)

#define CPU_FTR_CELL_TB_BUG		LONG_ASM_CONST(0x0000800000000000)

#define CPU_FTR_CELL_TB_BUG		LONG_ASM_CONST(0x0000800000000000)

#define CPU_FTR_SPURR			LONG_ASM_CONST(0x0001000000000000)

#define CPU_FTR_SPURR			LONG_ASM_CONST(0x0001000000000000)

#define CPU_FTR_DSCR			LONG_ASM_CONST(0x0002000000000000)

#define CPU_FTR_DSCR			LONG_ASM_CONST(0x0002000000000000)

#define CPU_FTR_1T_SEGMENT		LONG_ASM_CONST(0x0004000000000000)

#define CPU_FTR_NO_SLBIE_B		LONG_ASM_CONST(0x0008000000000000)

#define CPU_FTR_VSX			LONG_ASM_CONST(0x0010000000000000)

#define CPU_FTR_VSX			LONG_ASM_CONST(0x0010000000000000)

#define CPU_FTR_SAO			LONG_ASM_CONST(0x0020000000000000)

#define CPU_FTR_SAO			LONG_ASM_CONST(0x0020000000000000)

#define CPU_FTR_CP_USE_DCBTZ		LONG_ASM_CONST(0x0040000000000000)

#define CPU_FTR_CP_USE_DCBTZ		LONG_ASM_CONST(0x0040000000000000)
@@ -206,9 +200,10 @@ extern const char *powerpc_base_platform; 




#ifndef __ASSEMBLY__

#ifndef __ASSEMBLY__





#define CPU_FTR_PPCAS_ARCH_V2	(CPU_FTR_SLB | \

#define CPU_FTR_PPCAS_ARCH_V2	(CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)

				 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \



				 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)

#define MMU_FTR_PPCAS_ARCH_V2 	(MMU_FTR_SLB | MMU_FTR_TLBIEL | \

				 MMU_FTR_16M_PAGE)





/* We only set the altivec features if the kernel was compiled with altivec

/* We only set the altivec features if the kernel was compiled with altivec

 * support

 * support
@@ -408,38 +403,34 @@ extern const char *powerpc_base_platform; 
#define CPU_FTRS_POWER5	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER5	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \

	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \

	    CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)

	    CPU_FTR_POPCNTB)

#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \

	    CPU_FTR_COHERENT_ICACHE | \

	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \

	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \

	    CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \

	    CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)

#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_HVMODE_206 |\

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_HVMODE_206 |\

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \

	    CPU_FTR_COHERENT_ICACHE | \

	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \

	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \

	    CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \

	    CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)

#define CPU_FTRS_CELL	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_CELL	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \

	    CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \

	    CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \

	    CPU_FTR_UNALIGNED_LD_STD)

	    CPU_FTR_UNALIGNED_LD_STD)

#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \

	    CPU_FTR_PURR | CPU_FTR_REAL_LE)

	    CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)

#define CPU_FTRS_COMPATIBLE	(CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)

#define CPU_FTRS_COMPATIBLE	(CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)





#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \

#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \

	    CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \

		     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)

	    CPU_FTR_16M_PAGE)





#ifdef __powerpc64__

#ifdef __powerpc64__

#ifdef CONFIG_PPC_BOOK3E

#ifdef CONFIG_PPC_BOOK3E
@@ -449,7 +440,7 @@ extern const char *powerpc_base_platform; 
	    (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |	\

	    (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |	\

	    CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |	\

	    CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |	\

	    CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T |		\

	    CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T |		\

	    CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)

	    CPU_FTR_VSX)

#endif

#endif

#else

#else

enum {

enum {

arch/powerpc/include/asm/mmu.h

+48 −0
Original line number Original line Diff line number Diff line
@@ -70,6 +70,54 @@ 
 */

 */

#define MMU_FTR_USE_PAIRED_MAS		ASM_CONST(0x01000000)

#define MMU_FTR_USE_PAIRED_MAS		ASM_CONST(0x01000000)





/* MMU is SLB-based

 */

#define MMU_FTR_SLB			ASM_CONST(0x02000000)



/* Support 16M large pages

 */

#define MMU_FTR_16M_PAGE		ASM_CONST(0x04000000)



/* Supports TLBIEL variant

 */

#define MMU_FTR_TLBIEL			ASM_CONST(0x08000000)



/* Supports tlbies w/o locking

 */

#define MMU_FTR_LOCKLESS_TLBIE		ASM_CONST(0x10000000)



/* Large pages can be marked CI

 */

#define MMU_FTR_CI_LARGE_PAGE		ASM_CONST(0x20000000)



/* 1T segments available

 */

#define MMU_FTR_1T_SEGMENT		ASM_CONST(0x40000000)



/* Doesn't support the B bit (1T segment) in SLBIE

 */

#define MMU_FTR_NO_SLBIE_B		ASM_CONST(0x80000000)



/* MMU feature bit sets for various CPUs */

#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2	\

	MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2

#define MMU_FTRS_POWER4		MMU_FTRS_DEFAULT_HPTE_ARCH_V2

#define MMU_FTRS_PPC970		MMU_FTRS_POWER4

#define MMU_FTRS_POWER5		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE

#define MMU_FTRS_POWER6		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE

#define MMU_FTRS_POWER7		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | \

				MMU_FTR_TLBIE_206

#define MMU_FTRS_CELL		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \

				MMU_FTR_CI_LARGE_PAGE

#define MMU_FTRS_PA6T		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \

				MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B

#define MMU_FTRS_A2		MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \

				MMU_FTR_USE_TLBIVAX_BCAST | \

				MMU_FTR_LOCK_BCAST_INVAL | \

				MMU_FTR_USE_TLBRSRV | \

				MMU_FTR_USE_PAIRED_MAS | \

				MMU_FTR_TLBIEL | \

				MMU_FTR_16M_PAGE

#ifndef __ASSEMBLY__

#ifndef __ASSEMBLY__

#include <asm/cputable.h>

#include <asm/cputable.h>

arch/powerpc/include/asm/mmu_context.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -67,7 +67,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 
	 * sub architectures.

	 * sub architectures.

	 */

	 */

#ifdef CONFIG_PPC_STD_MMU_64

#ifdef CONFIG_PPC_STD_MMU_64

	if (cpu_has_feature(CPU_FTR_SLB))

	if (mmu_has_feature(MMU_FTR_SLB))

		switch_slb(tsk, next);

		switch_slb(tsk, next);

	else

	else

		switch_stab(tsk, next);

		switch_stab(tsk, next);

arch/powerpc/kernel/cputable.c

+19 −26
Original line number Original line Diff line number Diff line
@@ -201,7 +201,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "POWER4 (gp)",

		.cpu_name		= "POWER4 (gp)",

		.cpu_features		= CPU_FTRS_POWER4,

		.cpu_features		= CPU_FTRS_POWER4,

		.cpu_user_features	= COMMON_USER_POWER4,

		.cpu_user_features	= COMMON_USER_POWER4,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_POWER4,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 8,

		.num_pmcs		= 8,
@@ -216,7 +216,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "POWER4+ (gq)",

		.cpu_name		= "POWER4+ (gq)",

		.cpu_features		= CPU_FTRS_POWER4,

		.cpu_features		= CPU_FTRS_POWER4,

		.cpu_user_features	= COMMON_USER_POWER4,

		.cpu_user_features	= COMMON_USER_POWER4,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_POWER4,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 8,

		.num_pmcs		= 8,
@@ -232,7 +232,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_features		= CPU_FTRS_PPC970,

		.cpu_features		= CPU_FTRS_PPC970,

		.cpu_user_features	= COMMON_USER_POWER4 |

		.cpu_user_features	= COMMON_USER_POWER4 |

			PPC_FEATURE_HAS_ALTIVEC_COMP,

			PPC_FEATURE_HAS_ALTIVEC_COMP,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_PPC970,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 8,

		.num_pmcs		= 8,
@@ -250,7 +250,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_features		= CPU_FTRS_PPC970,

		.cpu_features		= CPU_FTRS_PPC970,

		.cpu_user_features	= COMMON_USER_POWER4 |

		.cpu_user_features	= COMMON_USER_POWER4 |

			PPC_FEATURE_HAS_ALTIVEC_COMP,

			PPC_FEATURE_HAS_ALTIVEC_COMP,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_PPC970,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 8,

		.num_pmcs		= 8,
@@ -286,7 +286,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_features		= CPU_FTRS_PPC970,

		.cpu_features		= CPU_FTRS_PPC970,

		.cpu_user_features	= COMMON_USER_POWER4 |

		.cpu_user_features	= COMMON_USER_POWER4 |

			PPC_FEATURE_HAS_ALTIVEC_COMP,

			PPC_FEATURE_HAS_ALTIVEC_COMP,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_PPC970,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 8,

		.num_pmcs		= 8,
@@ -304,7 +304,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_features		= CPU_FTRS_PPC970,

		.cpu_features		= CPU_FTRS_PPC970,

		.cpu_user_features	= COMMON_USER_POWER4 |

		.cpu_user_features	= COMMON_USER_POWER4 |

			PPC_FEATURE_HAS_ALTIVEC_COMP,

			PPC_FEATURE_HAS_ALTIVEC_COMP,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_PPC970,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 8,

		.num_pmcs		= 8,
@@ -320,7 +320,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "POWER5 (gr)",

		.cpu_name		= "POWER5 (gr)",

		.cpu_features		= CPU_FTRS_POWER5,

		.cpu_features		= CPU_FTRS_POWER5,

		.cpu_user_features	= COMMON_USER_POWER5,

		.cpu_user_features	= COMMON_USER_POWER5,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_POWER5,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 6,

		.num_pmcs		= 6,
@@ -340,7 +340,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "POWER5+ (gs)",

		.cpu_name		= "POWER5+ (gs)",

		.cpu_features		= CPU_FTRS_POWER5,

		.cpu_features		= CPU_FTRS_POWER5,

		.cpu_user_features	= COMMON_USER_POWER5_PLUS,

		.cpu_user_features	= COMMON_USER_POWER5_PLUS,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_POWER5,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 6,

		.num_pmcs		= 6,
@@ -356,7 +356,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "POWER5+ (gs)",

		.cpu_name		= "POWER5+ (gs)",

		.cpu_features		= CPU_FTRS_POWER5,

		.cpu_features		= CPU_FTRS_POWER5,

		.cpu_user_features	= COMMON_USER_POWER5_PLUS,

		.cpu_user_features	= COMMON_USER_POWER5_PLUS,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_POWER5,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 6,

		.num_pmcs		= 6,
@@ -373,7 +373,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "POWER5+",

		.cpu_name		= "POWER5+",

		.cpu_features		= CPU_FTRS_POWER5,

		.cpu_features		= CPU_FTRS_POWER5,

		.cpu_user_features	= COMMON_USER_POWER5_PLUS,

		.cpu_user_features	= COMMON_USER_POWER5_PLUS,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_POWER5,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.oprofile_cpu_type	= "ppc64/ibm-compat-v1",

		.oprofile_cpu_type	= "ppc64/ibm-compat-v1",
@@ -387,7 +387,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_features		= CPU_FTRS_POWER6,

		.cpu_features		= CPU_FTRS_POWER6,

		.cpu_user_features	= COMMON_USER_POWER6 |

		.cpu_user_features	= COMMON_USER_POWER6 |

			PPC_FEATURE_POWER6_EXT,

			PPC_FEATURE_POWER6_EXT,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_POWER6,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 6,

		.num_pmcs		= 6,
@@ -406,7 +406,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "POWER6 (architected)",

		.cpu_name		= "POWER6 (architected)",

		.cpu_features		= CPU_FTRS_POWER6,

		.cpu_features		= CPU_FTRS_POWER6,

		.cpu_user_features	= COMMON_USER_POWER6,

		.cpu_user_features	= COMMON_USER_POWER6,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_POWER6,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.oprofile_cpu_type	= "ppc64/ibm-compat-v1",

		.oprofile_cpu_type	= "ppc64/ibm-compat-v1",
@@ -419,8 +419,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "POWER7 (architected)",

		.cpu_name		= "POWER7 (architected)",

		.cpu_features		= CPU_FTRS_POWER7,

		.cpu_features		= CPU_FTRS_POWER7,

		.cpu_user_features	= COMMON_USER_POWER7,

		.cpu_user_features	= COMMON_USER_POWER7,

		.mmu_features		= MMU_FTR_HPTE_TABLE |

		.mmu_features		= MMU_FTRS_POWER7,

			MMU_FTR_TLBIE_206,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.oprofile_type		= PPC_OPROFILE_POWER4,

		.oprofile_type		= PPC_OPROFILE_POWER4,
@@ -435,8 +434,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "POWER7 (raw)",

		.cpu_name		= "POWER7 (raw)",

		.cpu_features		= CPU_FTRS_POWER7,

		.cpu_features		= CPU_FTRS_POWER7,

		.cpu_user_features	= COMMON_USER_POWER7,

		.cpu_user_features	= COMMON_USER_POWER7,

		.mmu_features		= MMU_FTR_HPTE_TABLE |

		.mmu_features		= MMU_FTRS_POWER7,

			MMU_FTR_TLBIE_206,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 6,

		.num_pmcs		= 6,
@@ -453,8 +451,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "POWER7+ (raw)",

		.cpu_name		= "POWER7+ (raw)",

		.cpu_features		= CPU_FTRS_POWER7,

		.cpu_features		= CPU_FTRS_POWER7,

		.cpu_user_features	= COMMON_USER_POWER7,

		.cpu_user_features	= COMMON_USER_POWER7,

		.mmu_features		= MMU_FTR_HPTE_TABLE |

		.mmu_features		= MMU_FTRS_POWER7,

			MMU_FTR_TLBIE_206,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 6,

		.num_pmcs		= 6,
@@ -473,7 +470,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_user_features	= COMMON_USER_PPC64 |

		.cpu_user_features	= COMMON_USER_PPC64 |

			PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |

			PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |

			PPC_FEATURE_SMT,

			PPC_FEATURE_SMT,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_CELL,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 4,

		.num_pmcs		= 4,
@@ -488,7 +485,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "PA6T",

		.cpu_name		= "PA6T",

		.cpu_features		= CPU_FTRS_PA6T,

		.cpu_features		= CPU_FTRS_PA6T,

		.cpu_user_features	= COMMON_USER_PA6T,

		.cpu_user_features	= COMMON_USER_PA6T,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_PA6T,

		.icache_bsize		= 64,

		.icache_bsize		= 64,

		.dcache_bsize		= 64,

		.dcache_bsize		= 64,

		.num_pmcs		= 6,

		.num_pmcs		= 6,
@@ -505,7 +502,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "POWER4 (compatible)",

		.cpu_name		= "POWER4 (compatible)",

		.cpu_features		= CPU_FTRS_COMPATIBLE,

		.cpu_features		= CPU_FTRS_COMPATIBLE,

		.cpu_user_features	= COMMON_USER_PPC64,

		.cpu_user_features	= COMMON_USER_PPC64,

		.mmu_features		= MMU_FTR_HPTE_TABLE,

		.mmu_features		= MMU_FTRS_DEFAULT_HPTE_ARCH_V2,

		.icache_bsize		= 128,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 6,

		.num_pmcs		= 6,
@@ -2020,11 +2017,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "A2 (>= DD2)",

		.cpu_name		= "A2 (>= DD2)",

		.cpu_features		= CPU_FTRS_A2,

		.cpu_features		= CPU_FTRS_A2,

		.cpu_user_features	= COMMON_USER_PPC64,

		.cpu_user_features	= COMMON_USER_PPC64,

		.mmu_features		= MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |

		.mmu_features		= MMU_FTRS_A2,

					  MMU_FTR_USE_TLBIVAX_BCAST |

					  MMU_FTR_LOCK_BCAST_INVAL |

					  MMU_FTR_USE_TLBRSRV |

					  MMU_FTR_USE_PAIRED_MAS,

		.icache_bsize		= 64,

		.icache_bsize		= 64,

		.dcache_bsize		= 64,

		.dcache_bsize		= 64,

		.num_pmcs		= 0,

		.num_pmcs		= 0,

arch/powerpc/kernel/entry_64.S

+4 −4
Original line number Original line Diff line number Diff line
@@ -468,10 +468,10 @@ BEGIN_FTR_SECTION 
  FTR_SECTION_ELSE_NESTED(95)

  FTR_SECTION_ELSE_NESTED(95)

	clrrdi	r6,r8,40	/* get its 1T ESID */

	clrrdi	r6,r8,40	/* get its 1T ESID */

	clrrdi	r9,r1,40	/* get current sp 1T ESID */

	clrrdi	r9,r1,40	/* get current sp 1T ESID */

  ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_1T_SEGMENT, 95)

  ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)

FTR_SECTION_ELSE

FTR_SECTION_ELSE

	b	2f

	b	2f

ALT_FTR_SECTION_END_IFSET(CPU_FTR_SLB)

ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)

	clrldi.	r0,r6,2		/* is new ESID c00000000? */

	clrldi.	r0,r6,2		/* is new ESID c00000000? */

	cmpd	cr1,r6,r9	/* or is new ESID the same as current ESID? */

	cmpd	cr1,r6,r9	/* or is new ESID the same as current ESID? */

	cror	eq,4*cr1+eq,eq

	cror	eq,4*cr1+eq,eq
@@ -485,7 +485,7 @@ BEGIN_FTR_SECTION 
	li	r9,MMU_SEGSIZE_1T	/* insert B field */

	li	r9,MMU_SEGSIZE_1T	/* insert B field */

	oris	r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h

	oris	r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h

	rldimi	r7,r9,SLB_VSID_SSIZE_SHIFT,0

	rldimi	r7,r9,SLB_VSID_SSIZE_SHIFT,0

END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)

END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)





	/* Update the last bolted SLB.  No write barriers are needed

	/* Update the last bolted SLB.  No write barriers are needed

	 * here, provided we only update the current CPU's SLB shadow

	 * here, provided we only update the current CPU's SLB shadow
@@ -497,7 +497,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) 
	std	r7,SLBSHADOW_STACKVSID(r9)  /* Save VSID */

	std	r7,SLBSHADOW_STACKVSID(r9)  /* Save VSID */

	std	r0,SLBSHADOW_STACKESID(r9)  /* Save ESID */

	std	r0,SLBSHADOW_STACKESID(r9)  /* Save ESID */





	/* No need to check for CPU_FTR_NO_SLBIE_B here, since when

	/* No need to check for MMU_FTR_NO_SLBIE_B here, since when

	 * we have 1TB segments, the only CPUs known to have the errata

	 * we have 1TB segments, the only CPUs known to have the errata

	 * only support less than 1TB of system memory and we'll never

	 * only support less than 1TB of system memory and we'll never

	 * actually hit this code path.

	 * actually hit this code path.